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/kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/
Dexynos5433-tmu.dtsi19 hysteresis = <1000>; /* millicelsius */
24 hysteresis = <1000>; /* millicelsius */
29 hysteresis = <1000>; /* millicelsius */
34 hysteresis = <1000>; /* millicelsius */
39 hysteresis = <1000>; /* millicelsius */
44 hysteresis = <1000>; /* millicelsius */
49 hysteresis = <1000>; /* millicelsius */
56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos5433-tmu.dtsi19 hysteresis = <1000>; /* millicelsius */
24 hysteresis = <1000>; /* millicelsius */
29 hysteresis = <1000>; /* millicelsius */
34 hysteresis = <1000>; /* millicelsius */
39 hysteresis = <1000>; /* millicelsius */
44 hysteresis = <1000>; /* millicelsius */
49 hysteresis = <1000>; /* millicelsius */
56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dintel_gt_clock_utils.c10 #define MHZ_12 12000000 /* 12MHz (24MHz/2), 83.333ns */
11 #define MHZ_12_5 12500000 /* 12.5MHz (25MHz/2), 80ns */
12 #define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */
49 gt->clock_frequency / 1000); in intel_gt_init_clock_frequency()
71 return div_u64_roundup(mul_u32_u32(count, 1000 * 1000 * 1000), in intel_gt_clock_interval_to_ns()
83 1000 * 1000 * 1000); in intel_gt_ns_to_clock_interval()
/kernel/linux/linux-6.6/drivers/clk/mvebu/
Darmada-39x.c24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
55 [0x0] = 666 * 1000 * 1000,
56 [0x2] = 800 * 1000 * 1000,
57 [0x3] = 800 * 1000 * 1000,
58 [0x4] = 1066 * 1000 * 1000,
59 [0x5] = 1066 * 1000 * 1000,
60 [0x6] = 1200 * 1000 * 1000,
[all …]
/kernel/linux/linux-5.10/drivers/clk/mvebu/
Darmada-39x.c24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
55 [0x0] = 666 * 1000 * 1000,
56 [0x2] = 800 * 1000 * 1000,
57 [0x3] = 800 * 1000 * 1000,
58 [0x4] = 1066 * 1000 * 1000,
59 [0x5] = 1066 * 1000 * 1000,
60 [0x6] = 1200 * 1000 * 1000,
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
Ddcn316_smu.c68 #define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
70 #define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
71 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
72 …SMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
73 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x09 ///< Set display phy clock frequency in MHZ …
74 …ine VBIOSSMC_MSG_GetFclkFrequency 0x0A ///< Get FCLK frequency, return frequemcy in MHZ
83 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
84 #define VBIOSSMC_MSG_GetDtbclkFreq 0x14 ///< Get DPREF clock frequency. Return in MHZ
85 …15 ///< Inform PMFW to turn on/off DTB clock arg = 1, turn DTB clock on 600MHz/ arg = 0 turn DTB c…
109 if (delay_us >= 1000) in dcn316_smu_wait_for_response()
[all …]
/kernel/linux/linux-5.10/drivers/cpufreq/
Dpxa3xx-cpufreq.c67 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
68 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
69 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
70 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
75 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
76 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
77 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
78 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
79 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
98 table[i].frequency = freqs[i].cpufreq_mhz * 1000; in setup_freqs_table()
[all …]
Ds5pv210-cpufreq.c87 /* APLL M,P,S values for 1G/800Mhz */
91 /* Use 800MHz when entering sleep mode */
92 #define SLEEP_FREQ (800 * 1000)
103 unsigned long refresh; /* DRAM refresh counter * 1000 */
125 {0, L0, 1000*1000},
126 {0, L1, 800*1000},
127 {0, L2, 400*1000},
128 {0, L3, 200*1000},
129 {0, L4, 100*1000},
175 /* L0 : [1000/200/100][166/83][133/66][200/200] */
[all …]
Dpmac32-cpufreq.c369 ppc_proc_freq = cur_freq * 1000ul; in pmac_cpufreq_target()
429 ppc_proc_freq = cur_freq * 1000ul; in pmac_cpufreq_resume()
503 * frequency, it claims it to be around 84Mhz on some models while in pmac_cpufreq_init_MacRISC3()
504 * it appears to be approx. 101Mhz on all. Let's hack around here... in pmac_cpufreq_init_MacRISC3()
530 low_freq = (*value) / 1000; in pmac_cpufreq_init_MacRISC3()
539 hi_freq = (*value) / 1000; in pmac_cpufreq_init_MacRISC3()
587 low_freq = (*value) / 1000; in pmac_cpufreq_init_750FX()
606 * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
607 * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
608 * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
[all …]
Delanfreq.c45 {1000, 0x02, 0x18},
56 {0, 0, 1000},
72 * at the moment. Frequencies from 1 to 33 MHz are generated
73 * the normal way, 66 and 99 MHz are called "Hyperspeed Mode"
74 * and have the rest of the chip running with 33 MHz.
89 /* Are we in CPU clock multiplied mode (66/99 MHz)? */ in elanfreq_get_cpu_frequency()
97 /* 33 MHz is not 32 MHz... */ in elanfreq_get_cpu_frequency()
101 return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000; in elanfreq_get_cpu_frequency()
117 * Bit 6 enables Hyperspeed Mode (66/100 MHz core frequency) in elanfreq_target()
124 udelay(1000); /* buffers have cleaned up */ in elanfreq_target()
[all …]
Ds3c2416-cpufreq.c98 return clk_get_rate(s3c_freq->armclk) / 1000; in s3c2416_cpufreq_get_speed()
106 if (clk_get_rate(s3c_freq->armdiv) / 1000 != freq) { in s3c2416_cpufreq_set_armdiv()
107 ret = clk_set_rate(s3c_freq->armdiv, freq * 1000); in s3c2416_cpufreq_set_armdiv()
131 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_enter_dvs()
191 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_leave_dvs()
193 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_leave_dvs()
196 clk_get_rate(s3c_freq->hclk) / 1000, ret); in s3c2416_cpufreq_leave_dvs()
202 clk_get_rate(s3c_freq->armdiv) / 1000); in s3c2416_cpufreq_leave_dvs()
242 ? clk_get_rate(s3c_freq->hclk) / 1000 in s3c2416_cpufreq_set_target()
298 s3c_freq->regulator_latency = 1 * 1000 * 1000; in s3c2416_cpufreq_cfg_regulator()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
Ddcn315_smu.c83 #define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
85 #define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
86 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
87 …SMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
88 #define VBIOSSMC_MSG_GetDtbclkFreq 0x09 ///< Get display dtb clock frequency in MHZ …
89 …BIOSSMC_MSG_SetDtbClk 0x0A ///< Set dtb clock frequency, return frequemcy in MHZ
91 #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0x0C ///< To ask PMFW turn off TMDP 48MHz refclk …
98 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
122 if (delay_us >= 1000) in dcn315_smu_wait_for_response()
123 msleep(delay_us/1000); in dcn315_smu_wait_for_response()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.c697 pll_settings->reference_freq * 1000, in calculate_ss()
1027 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17
1028 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340
1029 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758
1030 {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87
1031 {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516
1032 {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83
1033 {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527
1034 {257140, 257150, 257400, 1000, 1001}, //257.4Mhz -> 257.1429
1035 {296700, 296710, 297000, 1000, 1001}, //297Mhz -> 296.7033
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.c694 pll_settings->reference_freq * 1000, in calculate_ss()
983 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); in dcn31_program_pix_clk()
1119 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17
1120 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340
1121 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758
1122 {89910, 90000, 90000, 1000, 1001}, //90Mhz -> 89.91
1123 {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87
1124 {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516
1125 {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83
1126 {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527
[all …]
/kernel/linux/linux-6.6/drivers/cpufreq/
Ds5pv210-cpufreq.c87 /* APLL M,P,S values for 1G/800Mhz */
91 /* Use 800MHz when entering sleep mode */
92 #define SLEEP_FREQ (800 * 1000)
103 unsigned long refresh; /* DRAM refresh counter * 1000 */
125 {0, L0, 1000*1000},
126 {0, L1, 800*1000},
127 {0, L2, 400*1000},
128 {0, L3, 200*1000},
129 {0, L4, 100*1000},
175 /* L0 : [1000/200/100][166/83][133/66][200/200] */
[all …]
Dpmac32-cpufreq.c369 ppc_proc_freq = cur_freq * 1000ul; in pmac_cpufreq_target()
429 ppc_proc_freq = cur_freq * 1000ul; in pmac_cpufreq_resume()
502 * frequency, it claims it to be around 84Mhz on some models while in pmac_cpufreq_init_MacRISC3()
503 * it appears to be approx. 101Mhz on all. Let's hack around here... in pmac_cpufreq_init_MacRISC3()
529 low_freq = (*value) / 1000; in pmac_cpufreq_init_MacRISC3()
538 hi_freq = (*value) / 1000; in pmac_cpufreq_init_MacRISC3()
586 low_freq = (*value) / 1000; in pmac_cpufreq_init_750FX()
605 * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
606 * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
607 * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
[all …]
Dpxa3xx-cpufreq.c88 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
89 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
90 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
91 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
96 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
97 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
98 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
99 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
100 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
119 table[i].frequency = freqs[i].cpufreq_mhz * 1000; in setup_freqs_table()
[all …]
Delanfreq.c45 {1000, 0x02, 0x18},
56 {0, 0, 1000},
72 * at the moment. Frequencies from 1 to 33 MHz are generated
73 * the normal way, 66 and 99 MHz are called "Hyperspeed Mode"
74 * and have the rest of the chip running with 33 MHz.
89 /* Are we in CPU clock multiplied mode (66/99 MHz)? */ in elanfreq_get_cpu_frequency()
97 /* 33 MHz is not 32 MHz... */ in elanfreq_get_cpu_frequency()
101 return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000; in elanfreq_get_cpu_frequency()
117 * Bit 6 enables Hyperspeed Mode (66/100 MHz core frequency) in elanfreq_target()
124 udelay(1000); /* buffers have cleaned up */ in elanfreq_target()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Damdgpu_afmt.c35 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
36 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
37 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
38 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
39 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
40 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
41 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
42 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
43 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
44 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_afmt.c35 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
36 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
37 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
38 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
39 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
40 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
41 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
42 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
43 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
44 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-s3c/
Dcpu.h45 #ifndef MHZ
46 #define MHZ (1000*1000) macro
49 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Dcpu.h77 #define KHZ (1000)
80 #ifndef MHZ
81 #define MHZ (1000*1000) macro
84 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/kernel/linux/linux-6.6/drivers/gpu/drm/renesas/rcar-du/
Drcar_mipi_dsi.c31 #define MHZ(v) ((u32)((v) * 1000000U)) macro
102 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
103 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
104 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
105 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
106 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
107 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
108 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
109 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
110 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
[all …]
/kernel/linux/linux-6.6/drivers/clk/
Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/kernel/linux/linux-5.10/drivers/clk/
Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()

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