| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | uvd_v1_0.c | 32 * uvd_v1_0_get_rptr - get read pointer
35 * @ring: radeon_ring pointer
40 struct radeon_ring *ring) in uvd_v1_0_get_rptr() argument
46 * uvd_v1_0_get_wptr - get write pointer
49 * @ring: radeon_ring pointer
54 struct radeon_ring *ring) in uvd_v1_0_get_wptr() argument
60 * uvd_v1_0_set_wptr - set write pointer
63 * @ring: radeon_ring pointer
68 struct radeon_ring *ring) in uvd_v1_0_set_wptr() argument
70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); in uvd_v1_0_set_wptr()
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| D | uvd_v2_2.c | 32 * uvd_v2_2_fence_emit - emit an fence & trap command
37 * Write a fence and a trap command to the ring.
42 struct radeon_ring *ring = &rdev->ring[fence->ring]; in uvd_v2_2_fence_emit() local
43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit()
46 radeon_ring_write(ring, fence->seq); in uvd_v2_2_fence_emit()
47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit()
48 radeon_ring_write(ring, lower_32_bits(addr)); in uvd_v2_2_fence_emit()
49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit()
50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v2_2_fence_emit()
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| D | r600_dma.c | 35 * to the 3D engine (ring buffer, IBs, etc.), but the
37 * different form the PM4 format used by the 3D engine.
44 * r600_dma_get_rptr - get the current read pointer
47 * @ring: radeon ring pointer
52 struct radeon_ring *ring) in r600_dma_get_rptr() argument
56 if (rdev->wb.enabled) in r600_dma_get_rptr()
57 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
65 * r600_dma_get_wptr - get the current write pointer
68 * @ring: radeon ring pointer
73 struct radeon_ring *ring) in r600_dma_get_wptr() argument
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| D | uvd_v1_0.c | 32 * uvd_v1_0_get_rptr - get read pointer
35 * @ring: radeon_ring pointer
40 struct radeon_ring *ring) in uvd_v1_0_get_rptr() argument
46 * uvd_v1_0_get_wptr - get write pointer
49 * @ring: radeon_ring pointer
54 struct radeon_ring *ring) in uvd_v1_0_get_wptr() argument
60 * uvd_v1_0_set_wptr - set write pointer
63 * @ring: radeon_ring pointer
68 struct radeon_ring *ring) in uvd_v1_0_set_wptr() argument
70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); in uvd_v1_0_set_wptr()
[all …]
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| D | uvd_v2_2.c | 32 * uvd_v2_2_fence_emit - emit an fence & trap command
37 * Write a fence and a trap command to the ring.
42 struct radeon_ring *ring = &rdev->ring[fence->ring]; in uvd_v2_2_fence_emit() local
43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit()
46 radeon_ring_write(ring, fence->seq); in uvd_v2_2_fence_emit()
47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit()
48 radeon_ring_write(ring, lower_32_bits(addr)); in uvd_v2_2_fence_emit()
49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit()
50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v2_2_fence_emit()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/apm/xgene/ |
| D | xgene_enet_ring2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Driver
12 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_init() argument
14 u32 *ring_cfg = ring->state; in xgene_enet_ring_init()
15 u64 addr = ring->dma; in xgene_enet_ring_init()
17 if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) { in xgene_enet_ring_init()
18 ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); in xgene_enet_ring_init()
19 ring_cfg[3] |= SET_BIT(X2_DEQINTEN); in xgene_enet_ring_init()
27 ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize) in xgene_enet_ring_init()
34 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_set_type() argument
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| /kernel/linux/linux-5.10/drivers/net/ethernet/apm/xgene/ |
| D | xgene_enet_ring2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Driver
12 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_init() argument
14 u32 *ring_cfg = ring->state; in xgene_enet_ring_init()
15 u64 addr = ring->dma; in xgene_enet_ring_init()
17 if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) { in xgene_enet_ring_init()
18 ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); in xgene_enet_ring_init()
19 ring_cfg[3] |= SET_BIT(X2_DEQINTEN); in xgene_enet_ring_init()
27 ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize) in xgene_enet_ring_init()
34 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_set_type() argument
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v5_2.c | 74 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_2_get_reg_offset()
79 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_2_get_reg_offset()
83 base = adev->reg_offset[GC_HWIP][0][2]; in sdma_v5_2_get_reg_offset()
84 if (instance == 3) in sdma_v5_2_get_reg_offset()
92 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) in sdma_v5_2_ring_init_cond_exec() argument
96 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_2_ring_init_cond_exec()
97 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_2_ring_init_cond_exec()
98 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_2_ring_init_cond_exec()
99 amdgpu_ring_write(ring, 1); in sdma_v5_2_ring_init_cond_exec()
100 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ in sdma_v5_2_ring_init_cond_exec()
[all …]
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| D | uvd_v3_1.c | 38 * uvd_v3_1_ring_get_rptr - get read pointer
40 * @ring: amdgpu_ring pointer
44 static uint64_t uvd_v3_1_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v3_1_ring_get_rptr() argument
46 struct amdgpu_device *adev = ring->adev; in uvd_v3_1_ring_get_rptr()
52 * uvd_v3_1_ring_get_wptr - get write pointer
54 * @ring: amdgpu_ring pointer
58 static uint64_t uvd_v3_1_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v3_1_ring_get_wptr() argument
60 struct amdgpu_device *adev = ring->adev; in uvd_v3_1_ring_get_wptr()
66 * uvd_v3_1_ring_set_wptr - set write pointer
68 * @ring: amdgpu_ring pointer
[all …]
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| D | amdgpu_ring.c | 40 * Most engines on the GPU are fed via ring buffers. Ring
46 * pointers are equal, the ring is idle. When the host
47 * writes commands to the ring buffer, it increments the
53 * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission.
55 * @type: ring type for which to return the limit.
73 * amdgpu_ring_alloc - allocate space on the ring buffer
75 * @ring: amdgpu_ring structure holding ring information
76 * @ndw: number of dwords to allocate in the ring buffer
78 * Allocate @ndw dwords in the ring buffer (all asics).
81 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) in amdgpu_ring_alloc() argument
[all …]
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| D | mes_v10_1.c | 49 static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring) in mes_v10_1_ring_set_wptr() argument
51 struct amdgpu_device *adev = ring->adev; in mes_v10_1_ring_set_wptr()
53 if (ring->use_doorbell) { in mes_v10_1_ring_set_wptr()
54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, in mes_v10_1_ring_set_wptr()
55 ring->wptr); in mes_v10_1_ring_set_wptr()
56 WDOORBELL64(ring->doorbell_index, ring->wptr); in mes_v10_1_ring_set_wptr()
62 static u64 mes_v10_1_ring_get_rptr(struct amdgpu_ring *ring) in mes_v10_1_ring_get_rptr() argument
64 return *ring->rptr_cpu_addr; in mes_v10_1_ring_get_rptr()
67 static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring) in mes_v10_1_ring_get_wptr() argument
71 if (ring->use_doorbell) in mes_v10_1_ring_get_wptr()
[all …]
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| D | uvd_v4_2.c | 52 * uvd_v4_2_ring_get_rptr - get read pointer
54 * @ring: amdgpu_ring pointer
58 static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v4_2_ring_get_rptr() argument
60 struct amdgpu_device *adev = ring->adev; in uvd_v4_2_ring_get_rptr()
66 * uvd_v4_2_ring_get_wptr - get write pointer
68 * @ring: amdgpu_ring pointer
72 static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v4_2_ring_get_wptr() argument
74 struct amdgpu_device *adev = ring->adev; in uvd_v4_2_ring_get_wptr()
80 * uvd_v4_2_ring_set_wptr - set write pointer
82 * @ring: amdgpu_ring pointer
[all …]
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| D | amdgpu_ih.c | 24 #include <linux/dma-mapping.h>
30 * amdgpu_ih_ring_init - initialize the IH state
33 * @ih: ih ring to initialize
34 * @ring_size: ring size to allocate
38 * for the IH ring buffer.
47 /* Align ring size */ in amdgpu_ih_ring_init()
50 ih->ring_size = ring_size; in amdgpu_ih_ring_init()
51 ih->ptr_mask = ih->ring_size - 1; in amdgpu_ih_ring_init()
52 ih->rptr = 0; in amdgpu_ih_ring_init()
53 ih->use_bus_addr = use_bus_addr; in amdgpu_ih_ring_init()
[all …]
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| D | uvd_v5_0.c | 50 * uvd_v5_0_ring_get_rptr - get read pointer
52 * @ring: amdgpu_ring pointer
56 static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v5_0_ring_get_rptr() argument
58 struct amdgpu_device *adev = ring->adev; in uvd_v5_0_ring_get_rptr()
64 * uvd_v5_0_ring_get_wptr - get write pointer
66 * @ring: amdgpu_ring pointer
70 static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v5_0_ring_get_wptr() argument
72 struct amdgpu_device *adev = ring->adev; in uvd_v5_0_ring_get_wptr()
78 * uvd_v5_0_ring_set_wptr - set write pointer
80 * @ring: amdgpu_ring pointer
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v5_2.c | 67 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_2_get_reg_offset()
72 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_2_get_reg_offset()
76 base = adev->reg_offset[GC_HWIP][0][2]; in sdma_v5_2_get_reg_offset()
77 if (instance == 3) in sdma_v5_2_get_reg_offset()
87 switch (adev->asic_type) { in sdma_v5_2_init_golden_registers()
101 err = amdgpu_ucode_validate(sdma_inst->fw); in sdma_v5_2_init_inst_ctx()
105 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; in sdma_v5_2_init_inst_ctx()
106 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); in sdma_v5_2_init_inst_ctx()
107 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); in sdma_v5_2_init_inst_ctx()
109 if (sdma_inst->feature_version >= 20) in sdma_v5_2_init_inst_ctx()
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| D | uvd_v3_1.c | 38 * uvd_v3_1_ring_get_rptr - get read pointer
40 * @ring: amdgpu_ring pointer
44 static uint64_t uvd_v3_1_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v3_1_ring_get_rptr() argument
46 struct amdgpu_device *adev = ring->adev; in uvd_v3_1_ring_get_rptr()
52 * uvd_v3_1_ring_get_wptr - get write pointer
54 * @ring: amdgpu_ring pointer
58 static uint64_t uvd_v3_1_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v3_1_ring_get_wptr() argument
60 struct amdgpu_device *adev = ring->adev; in uvd_v3_1_ring_get_wptr()
66 * uvd_v3_1_ring_set_wptr - set write pointer
68 * @ring: amdgpu_ring pointer
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| D | uvd_v4_2.c | 52 * uvd_v4_2_ring_get_rptr - get read pointer
54 * @ring: amdgpu_ring pointer
58 static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v4_2_ring_get_rptr() argument
60 struct amdgpu_device *adev = ring->adev; in uvd_v4_2_ring_get_rptr()
66 * uvd_v4_2_ring_get_wptr - get write pointer
68 * @ring: amdgpu_ring pointer
72 static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v4_2_ring_get_wptr() argument
74 struct amdgpu_device *adev = ring->adev; in uvd_v4_2_ring_get_wptr()
80 * uvd_v4_2_ring_set_wptr - set write pointer
82 * @ring: amdgpu_ring pointer
[all …]
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| D | uvd_v5_0.c | 50 * uvd_v5_0_ring_get_rptr - get read pointer
52 * @ring: amdgpu_ring pointer
56 static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v5_0_ring_get_rptr() argument
58 struct amdgpu_device *adev = ring->adev; in uvd_v5_0_ring_get_rptr()
64 * uvd_v5_0_ring_get_wptr - get write pointer
66 * @ring: amdgpu_ring pointer
70 static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v5_0_ring_get_wptr() argument
72 struct amdgpu_device *adev = ring->adev; in uvd_v5_0_ring_get_wptr()
78 * uvd_v5_0_ring_set_wptr - set write pointer
80 * @ring: amdgpu_ring pointer
[all …]
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| D | amdgpu_ring.c | 40 * Most engines on the GPU are fed via ring buffers. Ring
46 * pointers are equal, the ring is idle. When the host
47 * writes commands to the ring buffer, it increments the
53 * amdgpu_ring_alloc - allocate space on the ring buffer
56 * @ring: amdgpu_ring structure holding ring information
57 * @ndw: number of dwords to allocate in the ring buffer
59 * Allocate @ndw dwords in the ring buffer (all asics).
62 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw) in amdgpu_ring_alloc() argument
66 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; in amdgpu_ring_alloc()
71 if (WARN_ON_ONCE(ndw > ring->max_dw)) in amdgpu_ring_alloc()
[all …]
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| /kernel/linux/linux-5.10/drivers/net/can/spi/mcp251xfd/ |
| D | mcp251xfd.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 * Marc Kleine-Budde <kernel@pengutronix.de>
15 #include <linux/can/rx-offload.h>
32 #define MCP251XFD_REG_CON_MODE_LISTENONLY 3
65 #define MCP251XFD_REG_DBTCFG_SJW_MASK GENMASK(3, 0)
116 #define MCP251XFD_REG_INT_MODIF BIT(3)
178 #define MCP251XFD_REG_TEFCON_TEFOVIE BIT(3)
184 #define MCP251XFD_REG_TEFSTA_TEFOVIF BIT(3)
196 #define MCP251XFD_REG_TXQCON_PLSIZE_20 3
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| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/ |
| D | qoriq-sec5.3-0.dtsi | 36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <4>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.3-job-ring",
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
53 compatible = "fsl,sec-v5.3-job-ring",
54 "fsl,sec-v5.0-job-ring",
55 "fsl,sec-v4.0-job-ring";
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | qoriq-sec5.3-0.dtsi | 36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <4>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.3-job-ring",
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
53 compatible = "fsl,sec-v5.3-job-ring",
54 "fsl,sec-v5.0-job-ring",
55 "fsl,sec-v4.0-job-ring";
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| /kernel/linux/linux-6.6/drivers/net/can/spi/mcp251xfd/ |
| D | mcp251xfd.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 * Marc Kleine-Budde <kernel@pengutronix.de>
16 #include <linux/can/rx-offload.h>
36 #define MCP251XFD_REG_CON_MODE_LISTENONLY 3
69 #define MCP251XFD_REG_DBTCFG_SJW_MASK GENMASK(3, 0)
120 #define MCP251XFD_REG_INT_MODIF BIT(3)
182 #define MCP251XFD_REG_TEFCON_TEFOVIE BIT(3)
188 #define MCP251XFD_REG_TEFSTA_TEFOVIF BIT(3)
200 #define MCP251XFD_REG_TXQCON_PLSIZE_20 3
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| /kernel/linux/linux-6.6/drivers/net/ethernet/freescale/enetc/ |
| D | enetc_cbdr.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2017-2019 NXP */
11 cbdr->bd_base = dma_alloc_coherent(dev, size, &cbdr->bd_dma_base, in enetc_setup_cbdr()
13 if (!cbdr->bd_base) in enetc_setup_cbdr()
14 return -ENOMEM; in enetc_setup_cbdr()
17 if (!IS_ALIGNED(cbdr->bd_dma_base, 128)) { in enetc_setup_cbdr()
18 dma_free_coherent(dev, size, cbdr->bd_base, in enetc_setup_cbdr()
19 cbdr->bd_dma_base); in enetc_setup_cbdr()
20 return -EINVAL; in enetc_setup_cbdr()
23 cbdr->next_to_clean = 0; in enetc_setup_cbdr()
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | uncore-io.json | 12 …y the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
27 …y the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
123 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
129 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
140 …serts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
151 …serts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
162 …serts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
167 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
173 …t 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugge…
184 …serts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
[all …]
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