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Searched +full:3 +full:cg +full:- +full:2019 (Results 1 – 19 of 19) sorted by relevance

/kernel/linux/linux-5.10/sound/soc/sof/intel/
D	hda-ipc.h	1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) / 6 Copyright(c) 2019 Intel Corporation. All rights reserved. 16 * - DIPCTDR (HIPCIDR) in sideband IPC (cAVS 1.8+) 17 * - DIPCT in cAVS 1.5 IPC 20 * - DIPCTDD (HIPCIDD) in sideband IPC (cAVS 1.8+) 21 * - DIPCTE in cAVS 1.5 IPC 28 /* Target, 0 - normal message, 1 - compact message(cAVS compatible) / 30 / Direction, 0 - request, 1 - response / 41 / Disable DMA tracing (0 - keep tracing, 1 - to disable DMA trace) / 43 / Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */ [all …]
/kernel/linux/linux-6.6/sound/soc/sof/intel/
D	hda-ipc.h	1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) / 6 Copyright(c) 2019 Intel Corporation. All rights reserved. 16 * - DIPCTDR (HIPCIDR) in sideband IPC (cAVS 1.8+) 17 * - DIPCT in cAVS 1.5 IPC 20 * - DIPCTDD (HIPCIDD) in sideband IPC (cAVS 1.8+) 21 * - DIPCTE in cAVS 1.5 IPC 28 /* Target, 0 - normal message, 1 - compact message(cAVS compatible) / 30 / Direction, 0 - request, 1 - response / 41 / Disable DMA tracing (0 - keep tracing, 1 - to disable DMA trace) / 43 / Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */ [all …]
/kernel/linux/linux-6.6/drivers/net/phy/
D	phy-c45.c	1 // SPDX-License-Identifier: GPL-2.0-only 11 #include "mdio-open-alliance.h" 14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities 21 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able() 26 phydev->pma_extable = val; in genphy_c45_baset1_able() 29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able() 33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support 48 * genphy_c45_pma_resume - wakes up the PMA module 54 return -EOPNOTSUPP; in genphy_c45_pma_resume() 62 * genphy_c45_pma_suspend - suspends the PMA module [all …]
/kernel/linux/linux-6.6/drivers/clk/tegra/
D	clk-dfll.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * clk-dfll.c - Tegra DFLL clock source common code 5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved. 12 * "CL-DVFS". To try to avoid confusion, this code refers to them 18 * DFLL can be operated in either open-loop mode or closed-loop mode. 19 * In open-loop mode, the DFLL generates an output clock appropriate 20 * to the supply voltage. In closed-loop mode, when configured with a 27 * performance-measurement code and any code that relies on the CPU 32 #include <linux/clk-provider.h> 49 #include "clk-dfll.h" [all …]
/kernel/linux/linux-5.10/drivers/clk/tegra/
D	clk-dfll.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * clk-dfll.c - Tegra DFLL clock source common code 5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved. 12 * "CL-DVFS". To try to avoid confusion, this code refers to them 18 * DFLL can be operated in either open-loop mode or closed-loop mode. 19 * In open-loop mode, the DFLL generates an output clock appropriate 20 * to the supply voltage. In closed-loop mode, when configured with a 27 * performance-measurement code and any code that relies on the CPU 32 #include <linux/clk-provider.h> 49 #include "clk-dfll.h" [all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
D	regd.c	1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 62 COUNTRY_CHPLAN_ENT("CG", RTW_CHPLAN_WORLD_ETSI1, RTW_REGD_ETSI), 272 if (!wiphy->bands[band]) in rtw_regd_apply_beaconing_flags() 275 sband = wiphy->bands[band]; in rtw_regd_apply_beaconing_flags() 276 for (i = 0; i < sband->n_channels; i++) { in rtw_regd_apply_beaconing_flags() 277 ch = &sband->channels[i]; in rtw_regd_apply_beaconing_flags() 280 MHZ_TO_KHZ(ch->center_freq)); in rtw_regd_apply_beaconing_flags() 284 ch->flags &= ~IEEE80211_CHAN_DISABLED; in rtw_regd_apply_beaconing_flags() 286 if (!(reg_rule->flags & NL80211_RRF_NO_IR)) in rtw_regd_apply_beaconing_flags() [all …]
/kernel/linux/linux-6.6/Documentation/networking/
D	ethtool-netlink.rst	27 wake-on-lan password) omitted. 37 number 1 but any non-zero value should be understood as "true" by recipient. 44 Attributes that need to be filled-in by device drivers and that are dumped to 91 representing bit values and mask of affected bits) and bit-by-bit (list of 94 Verbose (bit-by-bit) bitsets allow sending symbolic names for bits together 119 rounded up to a multiple of 32 bits. They consist of 32-bit words in host byte 134 Bit-by-bit form: nested (bitset) attribute contents: 136 +------------------------------------+--------+-----------------------------+ 138 +------------------------------------+--------+-----------------------------+ 140 +------------------------------------+--------+-----------------------------+ [all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw88/
D	regd.c	`1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 19 const struct rtw_regd __r = &__d->regd; \ 23 __r->regulatory->alpha2[0], \ 24 __r->regulatory->alpha2[1], \ 25 __r->regulatory->txpwr_regd_2g, \ 26 __r->regulatory->txpwr_regd_5g, \ 27 __r->dfs_region); \ 76 COUNTRY_REGD_ENT("CG", RTW_REGD_ETSI, RTW_REGD_ETSI), 283 struct rtw_dev rtwdev = hw->priv; in rtw_regd_apply_hw_cap_flags() [all …]`
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw89/
D	regd.c	1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 162 COUNTRY_REGD("CG", RTW89_ETSI, RTW89_ETSI, RTW89_NA), 282 ##_argv, __r->alpha2[0], __r->alpha2[1], \ 283 __r->txpwr_regd[RTW89_BAND_2G], \ 284 __r->txpwr_regd[RTW89_BAND_5G], \ 285 __r->txpwr_regd[RTW89_BAND_6G]); \ 291 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_regd_setup_unii4() 292 bool regd_allow_unii_4 = chip->support_unii4; in rtw89_regd_setup_unii4() 297 if (!chip->support_unii4) in rtw89_regd_setup_unii4() [all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
D	nv.c	2 * Copyright 2019 Advanced Micro Devices, Inc. 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 119 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 214 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in nv_query_video_codecs() 215 return -EINVAL; in nv_query_video_codecs() 217 switch (adev->ip_versions[UVD_HWIP][0]) { in nv_query_video_codecs() 218 case IP_VERSION(3, 0, 0): in nv_query_video_codecs() [all …]
D	gfx_v9_0.c	`193 /* SQC (3 ranges)/ 249 / TCC (5 sub-ranges)/ 280 / TCC range 3/ 312 / EA (3 sub-ranges)*/ 365 ((a) \| ((b) << 1) \| ((c) << 2) \| ((d) << 3)), \ 366 (((e) << 1) \| ((f) << 3) \| (g) \| ((h) << 2)), \ 724 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 725 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 726 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 727 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, [all …]`
D	gfx_v10_0.c	2 * Copyright 2019 Advanced Micro Devices, Inc. 3463 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3512 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); in gfx10_kiq_map_queues() 3513 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx10_kiq_map_queues() 3516 switch (ring->funcs->type) { in gfx10_kiq_map_queues() 3535 PACKET3_MAP_QUEUES_QUEUE(ring->queue) \| in gfx10_kiq_map_queues() 3536 PACKET3_MAP_QUEUES_PIPE(ring->pipe) \| in gfx10_kiq_map_queues() 3537 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) \| in gfx10_kiq_map_queues() 3542 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); in gfx10_kiq_map_queues() 3554 struct amdgpu_device *adev = kiq_ring->adev; in gfx10_kiq_unmap_queues() [all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
D	nv.c	2 * Copyright 2019 Advanced Micro Devices, Inc. 73 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg() 74 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg() 83 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg() 84 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg() 92 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg64() 93 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg64() 102 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg64() 103 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg64() 116 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_rreg() [all …]
D	gfx_v9_0.c	`186 /* SQC (3 ranges)/ 242 / TCC (5 sub-ranges)/ 273 / TCC range 3/ 305 / EA (3 sub-ranges)*/ 358 ((a) \| ((b) << 1) \| ((c) << 2) \| ((d) << 3)), \ 359 (((e) << 1) \| ((f) << 3) \| (g) \| ((h) << 2)), \ 717 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 718 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 719 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 720 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, [all …]`
D	gfx_v10_0.c	2 * Copyright 2019 Advanced Micro Devices, Inc. 1379 …scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_RE… in gfx_v10_rlcg_wreg() 1380 …scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v10_rlcg_wreg() 1381 …scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v10_rlcg_wreg() 1382 …scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v10_rlcg_wreg() 1383 …spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_IN… in gfx_v10_rlcg_wreg() 1385 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; in gfx_v10_rlcg_wreg() 1386 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; in gfx_v10_rlcg_wreg() 3196 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3236 struct amdgpu_device *adev = kiq_ring->adev; in gfx10_kiq_map_queues() [all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/
D	amdgpu_smu.c	2 * Copyright 2019 Advanced Micro Devices, Inc. 52 if (!smu->pm_enabled \|\| !smu->adev->pm.dpm_enabled) in smu_sys_get_pp_feature_mask() 53 return -EOPNOTSUPP; in smu_sys_get_pp_feature_mask() 55 mutex_lock(&smu->mutex); in smu_sys_get_pp_feature_mask() 59 mutex_unlock(&smu->mutex); in smu_sys_get_pp_feature_mask() 68 if (!smu->pm_enabled \|\| !smu->adev->pm.dpm_enabled) in smu_sys_set_pp_feature_mask() 69 return -EOPNOTSUPP; in smu_sys_set_pp_feature_mask() 71 mutex_lock(&smu->mutex); in smu_sys_set_pp_feature_mask() 75 mutex_unlock(&smu->mutex); in smu_sys_set_pp_feature_mask() 83 struct smu_context *smu = &adev->smu; in smu_get_status_gfxoff() [all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/
D	amdgpu_smu.c	2 * Copyright 2019 Advanced Micro Devices, Inc. 79 if (!smu->pm_enabled \|\| !smu->adev->pm.dpm_enabled) in smu_sys_get_pp_feature_mask() 80 return -EOPNOTSUPP; in smu_sys_get_pp_feature_mask() 90 if (!smu->pm_enabled \|\| !smu->adev->pm.dpm_enabled) in smu_sys_set_pp_feature_mask() 91 return -EOPNOTSUPP; in smu_sys_set_pp_feature_mask() 98 if (!smu->ppt_funcs->set_gfx_off_residency) in smu_set_residency_gfxoff() 99 return -EINVAL; in smu_set_residency_gfxoff() 106 if (!smu->ppt_funcs->get_gfx_off_residency) in smu_get_residency_gfxoff() 107 return -EINVAL; in smu_get_residency_gfxoff() 114 if (!smu->ppt_funcs->get_gfx_off_entrycount) in smu_get_entrycount_gfxoff() [all …]
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/
D	0005_linux_include.patch	`7 Change-Id: Icf23f02df7b566848af808b9eeaed889d1773e71 9 diff --git a/include/drm/bridge/cdns-mhdp.h b/include/drm/bridge/cdns-mhdp.h 12 --- /dev/null 13 +++ b/include/drm/bridge/cdns-mhdp.h 14 @@ -0,0 +1,921 @@ 15 +/* SPDX-License-Identifier: GPL-2.0 / 18 + Author: Chris Zhong <zyw@rock-chips.com> 39 +#include <sound/hdmi-codec.h> 313 +#define DPTX_SYS_CLK_RSTN_EN BIT(3) 321 +#define SOURCE_PKT_SYS_RSTN_EN BIT(3) [all …]`
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D	0036_linux_drivers_staging.patch	7 Change-Id: Ibe08cc261b06fe7f07187b5214df34e7cfed2515 9 diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig 11 --- a/drivers/staging/Kconfig 13 @@ -90,6 +90,8 @@ source "drivers/staging/greybus/Kconfig" 21 source "drivers/staging/mt7621-pci/Kconfig" 22 @@ -118,6 +120,8 @@ source "drivers/staging/wfx/Kconfig" 31 diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile 33 --- a/drivers/staging/Makefile 35 @@ -21,7 +21,7 @@ obj-$(CONFIG_IIO) += iio/ 36 obj-$(CONFIG_FB_SM750) += sm750fb/ [all …]