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/kernel/linux/linux-5.10/drivers/clk/qcom/
Dclk-spmi-pmic-div.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
24 struct clkdiv { struct
33 static inline struct clkdiv *to_clkdiv(struct clk_hw *hw) in to_clkdiv() argument
35 return container_of(hw, struct clkdiv, hw); in to_clkdiv()
43 return 1 << (div_factor - 1); in div_factor_to_div()
51 static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv) in is_spmi_pmic_clkdiv_enabled() argument
55 regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); in is_spmi_pmic_clkdiv_enabled()
61 __spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable, in __spmi_pmic_clkdiv_set_enable_state() argument
65 unsigned int ns = clkdiv->cxo_period_ns; in __spmi_pmic_clkdiv_set_enable_state()
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/kernel/linux/linux-6.6/drivers/clk/qcom/
Dclk-spmi-pmic-div.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
24 struct clkdiv { struct
33 static inline struct clkdiv *to_clkdiv(struct clk_hw *hw) in to_clkdiv() argument
35 return container_of(hw, struct clkdiv, hw); in to_clkdiv()
43 return 1 << (div_factor - 1); in div_factor_to_div()
51 static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv) in is_spmi_pmic_clkdiv_enabled() argument
55 regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); in is_spmi_pmic_clkdiv_enabled()
61 __spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable, in __spmi_pmic_clkdiv_set_enable_state() argument
65 unsigned int ns = clkdiv->cxo_period_ns; in __spmi_pmic_clkdiv_set_enable_state()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dqcom,spmi-clkdiv.txt1 Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
3 clkdiv configures the clock frequency of a set of outputs on the PMIC.
11 - compatible
14 Definition: must be "qcom,spmi-clkdiv".
16 - reg
18 Value type: <prop-encoded-array>
19 Definition: base address of CLKDIV peripherals.
21 - qcom,num-clkdivs
24 Definition: number of CLKDIV peripherals.
26 - clocks:
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Drenesas,emev2-smu.txt10 - compatible: Should be "renesas,emev2-smu"
11 - reg: Address and Size of SMU registers
21 - compatible: Should be "renesas,emev2-smu-clkdiv"
22 - reg: Byte offset from SMU base and Bit position in the register
23 - clocks: Parent clocks. Input clocks as described in clock-bindings.txt
24 - #clock-cells: Should be <0>
32 - compatible: Should be "renesas,emev2-smu-gclk"
33 - reg: Byte offset from SMU base and Bit position in the register
34 - clocks: Input clock as described in clock-bindings.txt
35 - #clock-cells: Should be <0>
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/kernel/linux/linux-5.10/drivers/media/rc/
Dtango-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/rc-core.h>
15 #define DRIVER_NAME "tango-ir"
60 v = readl_relaxed(ir->rc5_base + IR_NEC_DATA); in tango_ir_handle_nec()
62 rc_repeat(ir->rc); in tango_ir_handle_nec()
67 rc_keydown(ir->rc, proto, code, 0); in tango_ir_handle_nec()
74 data = readl_relaxed(ir->rc5_base + IR_RC5_DATA); in tango_ir_handle_rc5()
84 rc_keydown(ir->rc, RC_PROTO_RC5, code, toggle); in tango_ir_handle_rc5()
91 data0 = readl_relaxed(ir->rc6_base + RC6_DATA0); in tango_ir_handle_rc6()
92 data1 = readl_relaxed(ir->rc6_base + RC6_DATA1); in tango_ir_handle_rc6()
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/kernel/linux/linux-5.10/drivers/cpufreq/
Ds3c2412-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/soc/samsung/s3c-cpufreq-core.h>
23 #include <linux/soc/samsung/s3c-pm.h>
55 fclk = cfg->freq.fclk; in s3c2412_cpufreq_calcdivs()
56 armclk = cfg->freq.armclk; in s3c2412_cpufreq_calcdivs()
57 hclk_max = cfg->max.hclk; in s3c2412_cpufreq_calcdivs()
68 __func__, cfg->freq.fclk, cfg->freq.armclk, in s3c2412_cpufreq_calcdivs()
69 cfg->freq.hclk, cfg->freq.pclk); in s3c2412_cpufreq_calcdivs()
78 cfg->divs.arm_divisor = armdiv; in s3c2412_cpufreq_calcdivs()
85 cfg->freq.hclk = hclk = armdiv_clk / hdiv; in s3c2412_cpufreq_calcdivs()
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Ds3c2440-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2009 Simtec Electronics
23 #include <linux/soc/samsung/s3c-cpufreq-core.h>
24 #include <linux/soc/samsung/s3c-pm.h>
54 long diff = a - b; in within_khz()
56 return (diff >= -1000 && diff <= 1000); in within_khz()
60 * s3c2440_cpufreq_calcdivs - calculate divider settings
73 fclk = cfg->freq.fclk; in s3c2440_cpufreq_calcdivs()
74 armclk = cfg->freq.armclk; in s3c2440_cpufreq_calcdivs()
75 hclk_max = cfg->max.hclk; in s3c2440_cpufreq_calcdivs()
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Ds3c2410-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2008 Simtec Electronics
19 #include <linux/soc/samsung/s3c-cpufreq-core.h>
20 #include <linux/soc/samsung/s3c-pm.h>
28 /* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
32 u32 clkdiv = 0; in s3c2410_cpufreq_setdivs() local
34 if (cfg->divs.h_divisor == 2) in s3c2410_cpufreq_setdivs()
35 clkdiv |= S3C2410_CLKDIVN_HDIVN; in s3c2410_cpufreq_setdivs()
37 if (cfg->divs.p_divisor != cfg->divs.h_divisor) in s3c2410_cpufreq_setdivs()
38 clkdiv |= S3C2410_CLKDIVN_PDIVN; in s3c2410_cpufreq_setdivs()
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/kernel/linux/linux-6.6/drivers/spi/
Dspi-cavium.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define OCTEON_SPI_CFG(x) (x->regs.config)
27 #define OCTEON_SPI_STS(x) (x->regs.status)
28 #define OCTEON_SPI_TX(x) (x->regs.tx)
29 #define OCTEON_SPI_DAT0(x) (x->regs.data)
46 uint64_t clkdiv:13; member
78 uint64_t clkdiv:13;
85 uint64_t clkdiv:13; member
111 uint64_t clkdiv:13;
118 uint64_t clkdiv:13; member
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Dspi-cavium.c14 #include "spi-cavium.h"
24 mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p)); in octeon_spi_wait_ready()
33 struct spi_device *spi = msg->spi; in octeon_spi_do_transfer()
36 unsigned int clkdiv; in octeon_spi_do_transfer() local
44 mode = spi->mode; in octeon_spi_do_transfer()
48 clkdiv = p->sys_freq / (2 * xfer->speed_hz); in octeon_spi_do_transfer()
52 mpi_cfg.s.clkdiv = clkdiv; in octeon_spi_do_transfer()
61 p->cs_enax |= 1ull << (12 + spi_get_chipselect(spi, 0)); in octeon_spi_do_transfer()
62 mpi_cfg.u64 |= p->cs_enax; in octeon_spi_do_transfer()
64 if (mpi_cfg.u64 != p->last_cfg) { in octeon_spi_do_transfer()
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/kernel/linux/linux-5.10/drivers/spi/
Dspi-cavium.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define OCTEON_SPI_CFG(x) (x->regs.config)
27 #define OCTEON_SPI_STS(x) (x->regs.status)
28 #define OCTEON_SPI_TX(x) (x->regs.tx)
29 #define OCTEON_SPI_DAT0(x) (x->regs.data)
46 uint64_t clkdiv:13; member
78 uint64_t clkdiv:13;
85 uint64_t clkdiv:13; member
111 uint64_t clkdiv:13;
118 uint64_t clkdiv:13; member
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Dspi-cavium.c14 #include "spi-cavium.h"
24 mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p)); in octeon_spi_wait_ready()
33 struct spi_device *spi = msg->spi; in octeon_spi_do_transfer()
36 unsigned int clkdiv; in octeon_spi_do_transfer() local
44 mode = spi->mode; in octeon_spi_do_transfer()
48 clkdiv = p->sys_freq / (2 * xfer->speed_hz); in octeon_spi_do_transfer()
52 mpi_cfg.s.clkdiv = clkdiv; in octeon_spi_do_transfer()
60 if (spi->chip_select < 4) in octeon_spi_do_transfer()
61 p->cs_enax |= 1ull << (12 + spi->chip_select); in octeon_spi_do_transfer()
62 mpi_cfg.u64 |= p->cs_enax; in octeon_spi_do_transfer()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dqcom,spmi-clkdiv.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Stephen Boyd <sboyd@kernel.org>
20 const: qcom,spmi-clkdiv
27 - description: Board XO source
29 clock-names:
31 - const: xo
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/kernel/linux/linux-6.6/drivers/hwtracing/intel_th/
Dpti.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2016 Intel Corporation.
27 unsigned int clkdiv; member
46 return -EINVAL; in pti_width_mode()
54 return scnprintf(buf, PAGE_SIZE, "%d\n", pti_mode[pti->mode]); in mode_show()
72 pti->mode = ret; in mode_store()
85 return scnprintf(buf, PAGE_SIZE, "%d\n", pti->freeclk); in freerunning_clock_show()
100 pti->freeclk = !!val; in freerunning_clock_store()
113 return scnprintf(buf, PAGE_SIZE, "%d\n", 1u << pti->clkdiv); in clock_divider_show()
129 return -EINVAL; in clock_divider_store()
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/kernel/linux/linux-5.10/drivers/hwtracing/intel_th/
Dpti.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2016 Intel Corporation.
27 unsigned int clkdiv; member
46 return -EINVAL; in pti_width_mode()
54 return scnprintf(buf, PAGE_SIZE, "%d\n", pti_mode[pti->mode]); in mode_show()
72 pti->mode = ret; in mode_store()
85 return scnprintf(buf, PAGE_SIZE, "%d\n", pti->freeclk); in freerunning_clock_show()
100 pti->freeclk = !!val; in freerunning_clock_store()
113 return scnprintf(buf, PAGE_SIZE, "%d\n", 1u << pti->clkdiv); in clock_divider_show()
129 return -EINVAL; in clock_divider_store()
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/kernel/linux/linux-6.6/arch/arm/boot/dts/renesas/
Demev2.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <533000000>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Demev2.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <533000000>;
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/kernel/linux/linux-6.6/sound/soc/intel/skylake/
Dskl-nhlt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * skl-nhlt.c - Intel SKL Platform NHLT parsing
12 #include <sound/intel-nhlt.h>
14 #include "skl-i2s.h"
33 struct nhlt_acpi_table *nhlt = (struct nhlt_acpi_table *)skl->nhlt; in skl_nhlt_update_topology_bin()
35 struct device *dev = bus->dev; in skl_nhlt_update_topology_bin()
38 nhlt->header.oem_id, nhlt->header.oem_table_id, in skl_nhlt_update_topology_bin()
39 nhlt->header.oem_revision); in skl_nhlt_update_topology_bin()
41 snprintf(skl->tplg_name, sizeof(skl->tplg_name), "%x-%.6s-%.8s-%d%s", in skl_nhlt_update_topology_bin()
42 skl->pci_id, nhlt->header.oem_id, nhlt->header.oem_table_id, in skl_nhlt_update_topology_bin()
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/kernel/linux/linux-5.10/drivers/w1/masters/
Dmxc_w1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
22 # define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
45 writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_reset_bus()
53 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_reset_bus()
55 /* PST bit is valid after the RPP bit is self-cleared */ in mxc_w1_ds2_reset_bus()
73 writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_touch_bit()
81 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_touch_bit()
83 /* RDST bit is valid after the WR1/RD bit is self-cleared */ in mxc_w1_ds2_touch_bit()
95 unsigned int clkdiv; in mxc_w1_probe() local
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/kernel/linux/linux-6.6/drivers/w1/masters/
Dmxc_w1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
22 # define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
45 writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_reset_bus()
53 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_reset_bus()
55 /* PST bit is valid after the RPP bit is self-cleared */ in mxc_w1_ds2_reset_bus()
73 writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_touch_bit()
81 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_touch_bit()
83 /* RDST bit is valid after the WR1/RD bit is self-cleared */ in mxc_w1_ds2_touch_bit()
95 unsigned int clkdiv; in mxc_w1_probe() local
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/kernel/linux/linux-6.6/drivers/pwm/
Dpwm-tiehrpwm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
145 * set_prescale_div - Set up the prescaler divider function
153 unsigned int clkdiv, hspclkdiv; in set_prescale_div() local
155 for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { in set_prescale_div()
161 * CLKDIVIDER = (1), if clkdiv == 0 *OR* in set_prescale_div()
162 * (2 * clkdiv), if clkdiv != 0 in set_prescale_div()
168 *prescale_div = (1 << clkdiv) * in set_prescale_div()
171 *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | in set_prescale_div()
196 if (pc->polarity[chan] == PWM_POLARITY_INVERSED) in configure_polarity()
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/kernel/linux/linux-5.10/drivers/pwm/
Dpwm-tiehrpwm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
145 * set_prescale_div - Set up the prescaler divider function
153 unsigned int clkdiv, hspclkdiv; in set_prescale_div() local
155 for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { in set_prescale_div()
161 * CLKDIVIDER = (1), if clkdiv == 0 *OR* in set_prescale_div()
162 * (2 * clkdiv), if clkdiv != 0 in set_prescale_div()
168 *prescale_div = (1 << clkdiv) * in set_prescale_div()
171 *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | in set_prescale_div()
196 if (pc->polarity[chan] == PWM_POLARITY_INVERSED) in configure_polarity()
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/kernel/linux/linux-5.10/sound/soc/adi/
Daxi-spdif.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
66 return -EINVAL; in axi_spdif_trigger()
69 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_trigger()
80 unsigned int clkdiv, stat; in axi_spdif_hw_params() local
97 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), in axi_spdif_hw_params()
98 rate * 64 * 2) - 1; in axi_spdif_hw_params()
99 clkdiv <<= AXI_SPDIF_CTRL_CLKDIV_OFFSET; in axi_spdif_hw_params()
101 regmap_write(spdif->regmap, AXI_SPDIF_REG_STAT, stat); in axi_spdif_hw_params()
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/kernel/linux/linux-6.6/sound/soc/adi/
Daxi-spdif.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
66 return -EINVAL; in axi_spdif_trigger()
69 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_trigger()
80 unsigned int clkdiv, stat; in axi_spdif_hw_params() local
97 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), in axi_spdif_hw_params()
98 rate * 64 * 2) - 1; in axi_spdif_hw_params()
99 clkdiv <<= AXI_SPDIF_CTRL_CLKDIV_OFFSET; in axi_spdif_hw_params()
101 regmap_write(spdif->regmap, AXI_SPDIF_REG_STAT, stat); in axi_spdif_hw_params()
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/kernel/linux/linux-6.6/sound/soc/codecs/
Dadau1701.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
100 #define ADAU1707_CLKDIV_UNSET (-1U)
192 size = adau1701_register_size(&client->dev, reg); in adau1701_reg_write()
194 return -EINVAL; in adau1701_reg_write()
199 for (i = size + 1; i >= 2; --i) { in adau1701_reg_write()
210 return -EIO; in adau1701_reg_write()
223 size = adau1701_register_size(&client->dev, reg); in adau1701_reg_read()
225 return -EINVAL; in adau1701_reg_read()
230 msgs[0].addr = client->addr; in adau1701_reg_read()
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