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/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
Dcoresight-tmc.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma-mapping.h>
45 /* TMC_CTL - 0x020 */
47 /* TMC_STS - 0x00C */
53 * TMC_AXICTL - 0x110
55 * TMC AXICTL format for SoC-400
56 * Bits [0-1] : ProtCtrlBit0-1
57 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)
60 * Bits [8-11] : WrBurstLen
61 * Bits [12-31] : Reserved.
[all …]
Dcoresight-tmc-etr.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
17 #include "coresight-catu.h"
18 #include "coresight-etm-perf.h"
19 #include "coresight-priv.h"
20 #include "coresight-tmc.h"
30 * etr_perf_buffer - Perf buffer used for ETR
31 * @drvdata - The ETR drvdaga this buffer has been allocated for.
32 * @etr_buf - Actual buffer used by the ETR
33 * @pid - The PID this etr_perf_buffer belongs to.
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
5 obj-$(CONFIG_CORESIGHT) += coresight.o
6 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
7 coresight-sysfs.o coresight-syscfg.o coresight-config.o \
8 coresight-cfg-preload.o coresight-cfg-afdo.o \
9 coresight-syscfg-configfs.o coresight-trace-id.o
10 obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
11 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
12 coresight-tmc-etr.o
13 obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o
[all …]
Dcoresight-tmc-core.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/dma-mapping.h>
27 #include "coresight-priv.h"
28 #include "coresight-tmc.h"
36 struct coresight_device *csdev = drvdata->csdev; in tmc_wait_for_tmcready()
37 struct csdev_access *csa = &csdev->access; in tmc_wait_for_tmcready()
41 dev_err(&csdev->dev, in tmc_wait_for_tmcready()
42 "timeout while waiting for TMC to be Ready\n"); in tmc_wait_for_tmcready()
43 return -EBUSY; in tmc_wait_for_tmcready()
50 struct coresight_device *csdev = drvdata->csdev; in tmc_flush_and_stop()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
32 modules will be called coresight-funnel and coresight-replicator.
35 tristate "Coresight generic TMC driver"
41 trace router - ETR) or sink (embedded trace FIFO). The driver
46 module will be called coresight-tmc.
54 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
55 buffer by translating the addresses used by ETR to the physical address
56 by looking up the provided table. CATU can also be used in pass-through
60 module will be called coresight-catu.
67 responsible for bridging the gap between the on-chip coresight
[all …]
Dcoresight-catu.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-mapping.h>
17 #include "coresight-catu.h"
18 #include "coresight-priv.h"
19 #include "coresight-tmc.h"
22 dev_get_drvdata(csdev->dev.parent)
43 * ------------------------------------
44 * | Address [63-12] | SBZ | V|
45 * ------------------------------------
55 * SLADDR ===> x------------------x x--> x-----------------x
[all …]
/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
Dcoresight-tmc.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma-mapping.h>
45 /* TMC_CTL - 0x020 */
47 /* TMC_STS - 0x00C */
53 * TMC_AXICTL - 0x110
55 * TMC AXICTL format for SoC-400
56 * Bits [0-1] : ProtCtrlBit0-1
57 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)
60 * Bits [8-11] : WrBurstLen
61 * Bits [12-31] : Reserved.
[all …]
Dcoresight-tmc-etr.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
17 #include "coresight-catu.h"
18 #include "coresight-etm-perf.h"
19 #include "coresight-priv.h"
20 #include "coresight-tmc.h"
30 * etr_perf_buffer - Perf buffer used for ETR
31 * @drvdata - The ETR drvdaga this buffer has been allocated for.
32 * @etr_buf - Actual buffer used by the ETR
33 * @pid - The PID this etr_perf_buffer belongs to.
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
31 modules will be called coresight-funnel and coresight-replicator.
34 tristate "Coresight generic TMC driver"
40 trace router - ETR) or sink (embedded trace FIFO). The driver
45 module will be called coresight-tmc.
53 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
54 buffer by translating the addresses used by ETR to the physical address
55 by looking up the provided table. CATU can also be used in pass-through
59 module will be called coresight-catu.
66 responsible for bridging the gap between the on-chip coresight
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
5 obj-$(CONFIG_CORESIGHT) += coresight.o
6 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
7 coresight-sysfs.o
8 obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
9 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
10 coresight-tmc-etr.o
11 obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o
12 obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o
13 obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \
[all …]
Dcoresight-tmc-core.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/dma-mapping.h>
27 #include "coresight-priv.h"
28 #include "coresight-tmc.h"
37 if (coresight_timeout(drvdata->base, in tmc_wait_for_tmcready()
39 dev_err(&drvdata->csdev->dev, in tmc_wait_for_tmcready()
40 "timeout while waiting for TMC to be Ready\n"); in tmc_wait_for_tmcready()
48 ffcr = readl_relaxed(drvdata->base + TMC_FFCR); in tmc_flush_and_stop()
50 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); in tmc_flush_and_stop()
52 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); in tmc_flush_and_stop()
[all …]
Dcoresight-catu.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-mapping.h>
17 #include "coresight-catu.h"
18 #include "coresight-priv.h"
19 #include "coresight-tmc.h"
22 dev_get_drvdata(csdev->dev.parent)
43 * ------------------------------------
44 * | Address [63-12] | SBZ | V|
45 * ------------------------------------
55 * SLADDR ===> x------------------x x--> x-----------------x
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Darm,coresight-tmc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
24 FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
25 mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
[all …]
Darm,embedded-trace-extension.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Suzuki K Poulose <suzuki.poulose@arm.com>
12 - Mathieu Poirier <mathieu.poirier@linaro.org>
19 components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
26 pattern: "^ete([0-9a-f]+)$"
29 - const: arm,embedded-trace-extension
36 power-domains:
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/kernel/linux/linux-5.10/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-tmc1 What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr
10 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
14 Description: (Read) Defines the size, in 32-bit words, of the local RAM buffer.
17 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
21 Description: (Read) Shows the value held by the TMC status register. The value
24 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
28 Description: (Read) Shows the value held by the TMC RAM Read Pointer register
33 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
37 Description: (Read) Shows the value held by the TMC RAM Write Pointer register
42 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg
[all …]
/kernel/linux/linux-6.6/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-tmc1 What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr
10 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
14 Description: (Read) Defines the size, in 32-bit words, of the local RAM buffer.
17 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
21 Description: (Read) Shows the value held by the TMC status register. The value
24 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
28 Description: (Read) Shows the value held by the TMC RAM Read Pointer register
33 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
37 Description: (Read) Shows the value held by the TMC RAM Write Pointer register
42 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dcoresight.txt11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
23 Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
24 configuration. The configuration mode (ETB, ETF, ETR) is
26 "arm,coresight-tmc", "arm,primecell";
[all …]
/kernel/linux/linux-5.10/Documentation/trace/coresight/
Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
43 | |->### | ! | |->### | ! | ! . | || DAP ||
49 *****************************************************************<-|
63 | * ===== F =====<---------|
65 |-->:: CTI ::<!! === N ===
69 |------>&& ETB &&<......II I =======
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/hisilicon/
Dhi3660-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2016-2018 HiSilicon Ltd.
15 compatible = "arm,coresight-etm4x", "arm,primecell";
18 clock-names = "apb_pclk";
21 out-ports {
24 remote-endpoint =
32 compatible = "arm,coresight-etm4x", "arm,primecell";
35 clock-names = "apb_pclk";
38 out-ports {
41 remote-endpoint =
[all …]
Dhi6220-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
42 clock-names = "apb_pclk";
44 in-ports {
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhi3660-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2016-2018 Hisilicon Ltd.
15 compatible = "arm,coresight-etm4x", "arm,primecell";
18 clock-names = "apb_pclk";
21 out-ports {
24 remote-endpoint =
32 compatible = "arm,coresight-etm4x", "arm,primecell";
35 clock-names = "apb_pclk";
38 out-ports {
41 remote-endpoint =
[all …]
Dhi6220-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
42 clock-names = "apb_pclk";
44 in-ports {
[all …]
/kernel/linux/linux-5.10/drivers/acpi/
Dacpi_amba.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
25 {"ARMHC501", 0}, /* ARM CoreSight ETR */
29 {"ARMHC97C", 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */
59 if (adev->physical_node_count) in amba_handler_attach()
62 dev = amba_device_alloc(dev_name(&adev->dev), 0, 0); in amba_handler_attach()
64 dev_err(&adev->dev, "%s(): amba_device_alloc() failed\n", in amba_handler_attach()
66 return -ENOMEM; in amba_handler_attach()
75 switch (resource_type(rentry->res)) { in amba_handler_attach()
78 dev->res = *rentry->res; in amba_handler_attach()
[all …]
/kernel/linux/linux-6.6/Documentation/trace/coresight/
Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
43 | |->### | ! | |->### | ! | ! . | || DAP ||
49 *****************************************************************<-|
63 | * ===== F =====<---------|
65 |-->:: CTI ::<!! === N ===
69 |------>&& ETB &&<......II I =======
[all …]
/kernel/linux/linux-6.6/drivers/acpi/arm64/
Damba.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
24 {"ARMH0330", 0}, /* ARM DMA Controller DMA-330 */
25 {"ARMHC501", 0}, /* ARM CoreSight ETR */
29 {"ARMHC97C", 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */
60 if (adev->physical_node_count) in amba_handler_attach()
63 dev = amba_device_alloc(dev_name(&adev->dev), 0, 0); in amba_handler_attach()
65 dev_err(&adev->dev, "%s(): amba_device_alloc() failed\n", in amba_handler_attach()
67 return -ENOMEM; in amba_handler_attach()
76 switch (resource_type(rentry->res)) { in amba_handler_attach()
[all …]

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