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Searched +full:am3352 +full:- +full:phy +full:- +full:gmii +full:- +full:sel (Results 1 – 21 of 21) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dti,phy-gmii-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: CPSW Port's Interface Mode Selection PHY Tree Bindings
11 - Kishon Vijay Abraham I <kishon@ti.com>
20 +--------------+
21 +-------------------------------+ |SCM |
22 | CPSW | | +---------+ |
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dti,phy-gmii-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: CPSW Port's Interface Mode Selection PHY
11 - Kishon Vijay Abraham I <kishon@ti.com>
20 +--------------+
21 +-------------------------------+ |SCM |
22 | CPSW | | +---------+ |
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dcpsw-phy-sel.txt1 TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED)
2 -----------------------------------------------
5 - compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and
6 "ti,dra7xx-cpsw-phy-sel" for dra7xx platform
7 "ti,am43xx-cpsw-phy-sel" for am43xx platform
8 - reg : physical base address and size of the cpsw
10 - reg-names : names of the register map given in "reg" node
13 -rmii-clock-ext : If present, the driver will configure the RMII
18 phy_sel: cpsw-phy-sel@44e10650 {
19 compatible = "ti,am3352-cpsw-phy-sel";
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcpsw-phy-sel.txt1 TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED)
2 -----------------------------------------------
5 - compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and
6 "ti,dra7xx-cpsw-phy-sel" for dra7xx platform
7 "ti,am43xx-cpsw-phy-sel" for am43xx platform
8 - reg : physical base address and size of the cpsw
10 - reg-names : names of the register map given in "reg" node
13 -rmii-clock-ext : If present, the driver will configure the RMII
18 phy_sel: cpsw-phy-sel@44e10650 {
19 compatible = "ti,am3352-cpsw-phy-sel";
[all …]
/kernel/linux/linux-6.6/drivers/phy/ti/
Dphy-gmii-sel.c1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments CPSW Port's PHY Interface Mode selection Driver
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
7 * Based on cpsw-phy-sel.c driver created by Mugunthan V N <mugunthanvnm@ti.com>
16 #include <linux/phy.h>
17 #include <linux/phy/phy.h>
31 #define PHY_GMII_PORT(n) BIT((n) - 1)
43 struct phy *if_phy;
70 static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode) in phy_gmii_sel_mode() argument
72 struct phy_gmii_sel_phy_priv *if_phy = phy_get_drvdata(phy); in phy_gmii_sel_mode()
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/kernel/linux/linux-5.10/drivers/phy/ti/
Dphy-gmii-sel.c1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments CPSW Port's PHY Interface Mode selection Driver
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
7 * Based on cpsw-phy-sel.c driver created by Mugunthan V N <mugunthanvnm@ti.com>
16 #include <linux/phy.h>
17 #include <linux/phy/phy.h>
35 struct phy *if_phy;
58 static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode) in phy_gmii_sel_mode() argument
60 struct phy_gmii_sel_phy_priv *if_phy = phy_get_drvdata(phy); in phy_gmii_sel_mode()
61 const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data; in phy_gmii_sel_mode()
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/kernel/linux/linux-6.6/drivers/net/ethernet/ti/
Dcpsw-phy-sel.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/phy.h>
47 reg = readl(priv->gmii_sel); in cpsw_gmii_sel_am3352()
66 dev_warn(priv->dev, in cpsw_gmii_sel_am3352()
67 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n", in cpsw_gmii_sel_am3352()
79 if (priv->rmii_clock_external) { in cpsw_gmii_sel_am3352()
96 writel(reg, priv->gmii_sel); in cpsw_gmii_sel_am3352()
106 reg = readl(priv->gmii_sel); in cpsw_gmii_sel_dra7xx()
121 dev_warn(priv->dev, in cpsw_gmii_sel_dra7xx()
122 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n", in cpsw_gmii_sel_dra7xx()
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/kernel/linux/linux-5.10/drivers/net/ethernet/ti/
Dcpsw-phy-sel.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/phy.h>
48 reg = readl(priv->gmii_sel); in cpsw_gmii_sel_am3352()
67 dev_warn(priv->dev, in cpsw_gmii_sel_am3352()
68 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n", in cpsw_gmii_sel_am3352()
80 if (priv->rmii_clock_external) { in cpsw_gmii_sel_am3352()
97 writel(reg, priv->gmii_sel); in cpsw_gmii_sel_am3352()
107 reg = readl(priv->gmii_sel); in cpsw_gmii_sel_dra7xx()
122 dev_warn(priv->dev, in cpsw_gmii_sel_dra7xx()
123 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n", in cpsw_gmii_sel_dra7xx()
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/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Ddm814x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/bus/ti-sysc.h>
4 #include <dt-bindings/clock/dm814.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/dm814x.h>
10 interrupt-parent = <&intc>;
11 #address-cells = <1>;
12 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
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Dam33xx-l4.dtsi2 compatible = "ti,am33xx-l4-wkup", "simple-pm-bus";
3 power-domains = <&prm_wkup>;
5 clock-names = "fck";
10 reg-names = "ap", "la", "ia0", "ia1";
11 #address-cells = <1>;
12 #size-cells = <1>;
18 compatible = "simple-pm-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
28 compatible = "simple-pm-bus";
[all …]
Dam437x-l4.dtsi2 compatible = "ti,am4-l4-wkup", "simple-pm-bus";
3 power-domains = <&prm_wkup>;
5 clock-names = "fck";
10 reg-names = "ap", "la", "ia0", "ia1";
11 #address-cells = <1>;
12 #size-cells = <1>;
18 compatible = "simple-pm-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
28 compatible = "simple-pm-bus";
[all …]
Ddra7-l4.dtsi2 compatible = "ti,dra7-l4-cfg", "simple-pm-bus";
3 power-domains = <&prm_coreaon>;
5 clock-names = "fck";
9 reg-names = "ap", "la", "ia0";
10 #address-cells = <1>;
11 #size-cells = <1>;
17 compatible = "simple-pm-bus";
18 #address-cells = <1>;
19 #size-cells = <1>;
50 target-module@2000 { /* 0x4a002000, ap 3 08.0 */
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ddm814x.dtsi7 #include <dt-bindings/bus/ti-sysc.h>
8 #include <dt-bindings/clock/dm814.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/dm814x.h>
14 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
37 compatible = "arm,cortex-a8";
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Dam437x-l4.dtsi2 compatible = "ti,am4-l4-wkup", "simple-bus";
7 reg-names = "ap", "la", "ia0", "ia1";
8 #address-cells = <1>;
9 #size-cells = <1>;
15 compatible = "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
25 compatible = "simple-bus";
26 #address-cells = <1>;
27 #size-cells = <1>;
[all …]
Dam33xx-l4.dtsi2 compatible = "ti,am33xx-l4-wkup", "simple-bus";
7 reg-names = "ap", "la", "ia0", "ia1";
8 #address-cells = <1>;
9 #size-cells = <1>;
15 compatible = "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
25 compatible = "simple-bus";
26 #address-cells = <1>;
27 #size-cells = <1>;
[all …]
Ddra7-l4.dtsi2 compatible = "ti,dra7-l4-cfg", "simple-bus";
6 reg-names = "ap", "la", "ia0";
7 #address-cells = <1>;
8 #size-cells = <1>;
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
47 target-module@2000 { /* 0x4a002000, ap 3 08.0 */
48 compatible = "ti,sysc-omap4", "ti,sysc";
50 reg-names = "rev";
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/
Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
25 #address-cells = <2>;
26 #size-cells = <2>;
28 #interrupt-cells = <3>;
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Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
[all …]
Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
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