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Searched +full:emc +full:- +full:timings +full:- +full:1 (Results 1 – 25 of 44) sorted by relevance

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/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
77 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
86 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
151 struct emc_timing *timings; member
163 struct tegra_emc *emc = data; in tegra_emc_isr() local
167 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
173 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
177 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
182 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
188 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
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Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
151 ((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
161 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
192 (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)
193 #define EMC_REFCTRL_DISABLE_ALL(num) ((num) > 1 ? 0 : 2)
199 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
222 [1] = EMC_RFC,
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Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
44 #define PLLM_VCOB 1
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
80 ((new[n + 1] << EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ##\
522 { .bank = 1, .offset = EMC_MRW10, },
524 { .bank = 1, .offset = EMC_MRW11, },
[all …]
Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
21 #include <soc/tegra/emc.h>
264 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
274 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
275 #define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
282 DRAM_TYPE_DDR1 = 1,
476 struct emc_timing *timings; member
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
22 maxItems: 1
26 - description: external memory clock
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Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
[all …]
/kernel/linux/linux-6.6/drivers/memory/tegra/
Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/interconnect-provider.h>
96 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
106 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
112 #define EMC_FBIO_CFG5_DRAM_TYPE GENMASK(1, 0)
120 #define EMC_PWR_GATHER_CLEAR (1 << 8)
206 struct emc_timing *timings; member
216 * There are multiple sources in the EMC driver which could request
221 /* protect shared rate-change code path */
237 struct tegra_emc *emc = data; in tegra_emc_isr() local
[all …]
Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
162 ((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
172 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
203 (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)
204 #define EMC_REFCTRL_DISABLE_ALL(num) ((num) > 1 ? 0 : 2)
210 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
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Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
44 #define PLLM_VCOB 1
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
80 ((new[n + 1] << EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ##\
522 { .bank = 1, .offset = EMC_MRW10, },
524 { .bank = 1, .offset = EMC_MRW11, },
[all …]
Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
271 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
281 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
282 #define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
289 DRAM_TYPE_DDR1 = 1,
495 struct emc_timing *timings; member
507 * There are multiple sources in the EMC driver which could request
512 /* protect shared rate-change code path */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
22 maxItems: 1
26 - description: external memory clock
[all …]
Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
[all …]
Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
25 maxItems: 1
28 maxItems: 1
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/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
24 #include <soc/tegra/emc.h>
46 * List of clock sources for various parents the EMC clock can have.
53 #define EMC_SRC_PLL_C 1
78 struct tegra_emc *emc; member
81 struct emc_timing *timings; member
101 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
109 * safer since things have EMC rate floors. Also don't touch parent_rate
[all …]
/kernel/linux/linux-6.6/drivers/clk/tegra/
Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
47 * List of clock sources for various parents the EMC clock can have.
54 #define EMC_SRC_PLL_C 1
79 struct tegra_emc *emc; member
82 struct emc_timing *timings; member
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
113 * safer since things have EMC rate floors. Also don't touch parent_rate
125 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-car.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
20 - #reset-cells : Should be 1.
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
7 * Tilapia's memory timings are pretty much the same as the Grouper's
9 * these differentiating timings are overridden here for Tilapia.
12 memory-controller@7000f400 {
13 emc-timings-0 {
14 timing-667000000 {
15 clock-frequency = <667000000>;
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
[all …]
Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
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/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
7 * Tilapia's memory timings are pretty much the same as the Grouper's
9 * these differentiating timings are overridden here for Tilapia.
12 memory-controller@7000f400 {
13 emc-timings-0 {
14 timing-667000000 {
15 clock-frequency = <667000000>;
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
[all …]
Dtegra30-asus-tf201.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
19 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 /* Azurewave AW-NH615 BCM4329B1 */
[all …]
Dtegra30-asus-tf300t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300t-init-hog {
13 gpio-hog;
15 output-low;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
Dtegra30-asus-tf300tg.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300tg-init-hog {
13 gpio-hog;
16 <TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>,
25 <TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>,
28 output-low;
39 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
52 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
[all …]
Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]

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