Searched full:fdiv (Results 1 – 15 of 15) sorted by relevance
| /arkcompiler/ets_runtime/ecmascript/compiler/ |
| D | lcr_opcodes.h | 30 … V(Fdiv, FDIV, GateFlags::NONE_FLAG, 0, 0, 2) \
|
| D | number_speculative_lowering.cpp | 370 result = builder_.BinaryArithmetic(circuit_->Fdiv(), in VisitNumberDiv()
|
| D | gate.cpp | 141 case OpCode::FDIV: in CheckValueInput()
|
| D | circuit_ir_specification.md | 351 * **FDIV**: returns the quotient of its two floating-point operands.
|
| D | circuit_builder.h | 76 V(DoubleDiv, Fdiv, MachineType::F64) \
|
| D | instruction_combine.cpp | 46 case OpCode::FDIV: in VisitGate()
|
| /arkcompiler/runtime_core/static_core/compiler/optimizer/ir_builder/ |
| D | inst_templates.yaml | 16 % regex_arithm = /(fdiv|fmod|add|sub|mul|and|or|xor|ashr|shr|shl|neg|not)[2i]?(iv)?/
19 % opc = opc[1].capitalize.gsub('Ashr', 'AShr').gsub('Fdiv', 'Div').gsub('Fmod', 'Mod')
68 % regex_arithm = /(fdiv|fmod|add|sub|mul|and|or|xor|ashr|shr|shl)2v$/
71 % opc = opc[1].capitalize.gsub('Ashr', 'AShr').gsub('Fdiv', 'Div').gsub('Fmod', 'Mod')
|
| /arkcompiler/runtime_core/static_core/compiler/optimizer/templates/ |
| D | inst_builder_gen.cpp.erb | 96 /(fdiv|fmod|add|sub|mul|and|or|xor|ashr|shr|shl|neg|not)[2i]?(iv)?$/ => "binop",
98 /(fdiv|fmod|add|sub|mul|and|or|xor|ashr|shr|shl)2v$/ => "binop_v2",
|
| /arkcompiler/runtime_core/compiler/optimizer/ir_builder/ |
| D | inst_templates.yaml | 16 % regex_arithm = /(fdiv|fmod|add|sub|mul|and|or|xor|ashr|shr|shl|neg|not)[2i]?/
19 % opc = opc[1].capitalize.gsub('Ashr', 'AShr').gsub('Fdiv', 'Div').gsub('Fmod', 'Mod')
|
| /arkcompiler/runtime_core/compiler/optimizer/templates/ |
| D | inst_builder_gen.cpp.erb | 106 /(fdiv|fmod|add|sub|mul|and|or|xor|ashr|shr|shl|neg|not)[2i]?$/ => "binop",
|
| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/aarch64/ |
| D | aarch64_md.def | 448 …::Reg32FD,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS},CANTHROW,kLtAdvsimdDivS,"fdiv","0,1,2",1,kFloatDa…
450 …::Reg64FD,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS},CANTHROW,kLtAdvsimdDivD,"fdiv","0,1,2",1,kFloatDa…
|
| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/ |
| D | litecg_ir_builder.cpp | 387 case OpCode::FDIV: in HandleBB()
389 InsertUsedOpcodeSet(usedOpcodeSet, OpCode::FDIV); in HandleBB()
|
| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/llvm/ |
| D | llvm_ir_builder.cpp | 188 {OpCode::FDIV, &LLVMIRBuilder::HandleFloatDiv}, in InitializeHandlers()
|
| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch64/ |
| D | encode.cpp | 1633 GetMasm()->Fdiv(VixlVReg(dst), VixlVReg(src0), VixlVReg(src1)); in EncodeDiv()
|
| /arkcompiler/runtime_core/static_core/libllvmbackend/lowering/ |
| D | llvm_ir_constructor.cpp | 3781 n = ctor->CreateBinaryOp(inst, llvm::Instruction::FDiv); in VisitDiv()
|