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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/
Dimx219.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
34 VANA-supply:
[all …]
Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
[all …]
Dov8856.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dongchun Zhu <dongchun.zhu@mediatek.com>
13 description: |-
14 The Omnivision OV8856 is a high performance, 1/4-inch, 8 megapixel, CMOS
15 image sensor that delivers 3264x2448 at 30fps. It provides full-frame,
16 sub-sampled, and windowed 10-bit MIPI images in various formats via the
18 through I2C and two-wire SCCB. The sensor output is available via CSI-2
19 serial data output (up to 4-lane).
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/i2c/
Dimx219.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
34 VANA-supply:
[all …]
Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
[all …]
Disil,isl79987.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intersil ISL79987 Analog to MIPI CSI-2 decoder
10 - Michael Tretter <m.tretter@pengutronix.de>
11 - Marek Vasut <marex@denx.de>
14 The Intersil ISL79987 is an analog to MIPI CSI-2 decoder which is capable of
15 receiving up to four analog stream and multiplexing them into up to four MIPI
16 CSI-2 virtual channels, using one MIPI clock lane and 1/2 data lanes.
21 - isil,isl79987
[all …]
Dov8856.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sakari Ailus <sakari.ailus@linux.intel.com>
13 description: |-
14 The Omnivision OV8856 is a high performance, 1/4-inch, 8 megapixel, CMOS
15 image sensor that delivers 3264x2448 at 30fps. It provides full-frame,
16 sub-sampled, and windowed 10-bit MIPI images in various formats via the
18 through I2C and two-wire SCCB. The sensor output is available via CSI-2
19 serial data output (up to 4-lane).
[all …]
/kernel/linux/linux-5.10/arch/mips/cavium-octeon/executive/
Dcvmx-helper-errata.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * contains functions called by cvmx-helper to workaround known
40 #include <asm/octeon/cvmx-helper-jtag.h>
43 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
53 /* We need to load all four lanes of the QLM, a total of 1072 bits */ in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
56 * Each lane has 268 bits. We need to set in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
[all …]
/kernel/linux/linux-6.6/arch/mips/cavium-octeon/executive/
Dcvmx-helper-errata.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * contains functions called by cvmx-helper to workaround known
40 #include <asm/octeon/cvmx-helper-jtag.h>
43 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
53 /* We need to load all four lanes of the QLM, a total of 1072 bits */ in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
56 * Each lane has 268 bits. We need to set in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
14 The PS8640 is a low power MIPI-to-eDP video format converter supporting
16 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
17 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
19 3.24Gbit/sec per lane.
29 powerdown-gpios:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
18 3.24Gbit/sec per lane.
28 powerdown-gpios:
32 reset-gpios:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
[all …]
Dxlnx,zynqmp-psgtr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
18 "#phy-cells":
23 - description: The GTR lane
26 - description: The PHY type
28 - PHY_TYPE_DP
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../snps,dw-pcie.yaml
[all …]
Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../designware-pcie.txt
[all …]
Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
[all …]
Dxlnx,zynqmp-psgtr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
18 "#phy-cells":
23 - description: The GTR lane
26 - description: The PHY type
28 - PHY_TYPE_DP
[all …]
/kernel/linux/linux-5.10/drivers/nvdimm/
Dbtt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2014-2015, Intel Corporation.
49 * A log group represents one log 'lane', and consists of four log entries.
50 * Two of the four entries are valid entries, and the remaining two are
60 * +-----------------+-----------------+
64 * +-----------------------------------+
68 * +-----------------+-----------------+
71 * +-----------------+-----------------+
75 * +-----------------------------------+
79 * +-----------------+-----------------+
[all …]
/kernel/linux/linux-6.6/drivers/nvdimm/
Dbtt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2014-2015, Intel Corporation.
48 * A log group represents one log 'lane', and consists of four log entries.
49 * Two of the four entries are valid entries, and the remaining two are
59 * +-----------------+-----------------+
63 * +-----------------------------------+
67 * +-----------------+-----------------+
70 * +-----------------+-----------------+
74 * +-----------------------------------+
78 * +-----------------+-----------------+
[all …]
/kernel/linux/linux-6.6/drivers/phy/tegra/
Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
280 writel(value, priv->ao_regs + offset); in ao_writel()
285 return readl(priv->ao_regs + offset); in ao_readl()
304 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
306 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
307 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
308 usb2->base.index = index; in tegra186_usb2_lane_probe()
309 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
24 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
30 #define PPI_LANEENABLE 0x0134 /* Enables each lane */
32 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
33 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
34 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */
35 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
40 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
121 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
28 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
34 #define PPI_LANEENABLE 0x0134 /* Enables each lane */
36 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
37 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
38 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */
39 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
43 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
44 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
125 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
[all …]

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