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/kernel/linux/linux-6.6/drivers/gpu/drm/vc4/
Dvc4_hvs.c7 * DOC: VC4 HVS module.
9 * The Hardware Video Scaler (HVS) is the piece of hardware that does
16 * There is a single global HVS, with multiple output FIFOs that can
18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for
70 void vc4_hvs_dump_state(struct vc4_hvs *hvs) in vc4_hvs_dump_state() argument
72 struct drm_device *drm = &hvs->vc4->base; in vc4_hvs_dump_state()
73 struct drm_printer p = drm_info_printer(&hvs->pdev->dev); in vc4_hvs_dump_state()
79 drm_print_regset32(&p, &hvs->regset); in vc4_hvs_dump_state()
81 DRM_INFO("HVS ctx:\n"); in vc4_hvs_dump_state()
85 readl((u32 __iomem *)hvs->dlist + i + 0), in vc4_hvs_dump_state()
[all …]
Dvc4_plane.c9 * Each DRM plane is a layer of pixels being scanned out by the HVS.
11 * At atomic modeset check time, we compute the HVS display element
15 * into the region of the HVS that it has allocated for us.
35 u32 hvs; /* HVS_FORMAT_* */ member
42 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
48 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
54 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
60 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
66 .hvs = HVS_PIXEL_FORMAT_RGB565,
72 .hvs = HVS_PIXEL_FORMAT_RGB565,
[all …]
Dvc4_crtc.c12 * the HVS at that timing, and feeds it to the encoder.
16 * responsible for writing the display list for the HVS channel that
85 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_cob_allocation() local
105 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_scanout_position() local
122 * pixelvalve by the HVS, and also the scaler status. in vc4_crtc_get_scanout_position()
132 /* Vertical position of hvs composed scanline. */ in vc4_crtc_get_scanout_position()
140 if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2) in vc4_crtc_get_scanout_position()
145 /* This is the offset we need for translating hvs -> pv scanout pos. */ in vc4_crtc_get_scanout_position()
151 /* HVS more than fifo_lines into frame for compositing? */ in vc4_crtc_get_scanout_position()
155 * from HVS. The actual PV scanout can not trail behind more in vc4_crtc_get_scanout_position()
[all …]
Dvc4_kms.c137 struct vc4_hvs *hvs = vc4->hvs; in vc4_ctm_commit() local
211 struct vc4_hvs *hvs = vc4->hvs; in vc4_hvs_pv_muxing_commit() local
252 struct vc4_hvs *hvs = vc4->hvs; in vc5_hvs_pv_muxing_commit() local
327 struct vc4_hvs *hvs = vc4->hvs; in vc4_atomic_commit_tail() local
350 vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel); in vc4_atomic_commit_tail()
376 500000000, hvs->max_core_rate); in vc4_atomic_commit_tail()
384 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); in vc4_atomic_commit_tail()
411 hvs->max_core_rate, in vc4_atomic_commit_tail()
417 * Request a clock rate based on the current HVS in vc4_atomic_commit_tail()
420 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); in vc4_atomic_commit_tail()
[all …]
Dvc4_drv.h90 struct vc4_hvs *hvs; member
204 * demanding in term of memory or HVS bandwidth which is hard to guess
326 /* Memory manager for the LBM memory used by HVS scaling. */
435 /* Load of this plane on the HVS block. The load is expressed in HVS
498 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */
501 /* Which output of the HVS this pixelvalve sources from. */
558 * set in the HVS for that CRTC. Protected by @irq_lock, and
565 * @current_hvs_channel: HVS channel currently assigned to the
633 readl(hvs->regs + (offset)); \
639 writel(val, hvs->regs + (offset)); \
[all …]
Dvc4_drv.c277 { .compatible = "brcm,bcm2711-hvs" },
278 { .compatible = "brcm,bcm2835-hvs" },
415 * but after the HVS to set the possible_crtc field properly
416 * - The HDMI driver needs to be bound after the HVS so that we can
417 * lookup the HVS maximum core clock rate and figure out if we
/kernel/linux/linux-5.10/drivers/gpu/drm/vc4/
Dvc4_hvs.c7 * DOC: VC4 HVS module.
9 * The Hardware Video Scaler (HVS) is the piece of hardware that does
16 * There is a single global HVS, with multiple output FIFOs that can
18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for
70 struct drm_printer p = drm_info_printer(&vc4->hvs->pdev->dev); in vc4_hvs_dump_state()
73 drm_print_regset32(&p, &vc4->hvs->regset); in vc4_hvs_dump_state()
75 DRM_INFO("HVS ctx:\n"); in vc4_hvs_dump_state()
79 readl((u32 __iomem *)vc4->hvs->dlist + i + 0), in vc4_hvs_dump_state()
80 readl((u32 __iomem *)vc4->hvs->dlist + i + 1), in vc4_hvs_dump_state()
81 readl((u32 __iomem *)vc4->hvs->dlist + i + 2), in vc4_hvs_dump_state()
[all …]
Dvc4_plane.c9 * Each DRM plane is a layer of pixels being scanned out by the HVS.
11 * At atomic modeset check time, we compute the HVS display element
15 * into the region of the HVS that it has allocated for us.
33 u32 hvs; /* HVS_FORMAT_* */ member
39 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
45 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
51 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
57 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
63 .hvs = HVS_PIXEL_FORMAT_RGB565,
68 .hvs = HVS_PIXEL_FORMAT_RGB565,
[all …]
Dvc4_crtc.c12 * the HVS at that timing, and feeds it to the encoder.
16 * responsible for writing the display list for the HVS channel that
106 * pixelvalve by the HVS, and also the scaler status. in vc4_crtc_get_scanout_position()
116 /* Vertical position of hvs composed scanline. */ in vc4_crtc_get_scanout_position()
129 /* This is the offset we need for translating hvs -> pv scanout pos. */ in vc4_crtc_get_scanout_position()
135 /* HVS more than fifo_lines into frame for compositing? */ in vc4_crtc_get_scanout_position()
139 * from HVS. The actual PV scanout can not trail behind more in vc4_crtc_get_scanout_position()
141 * in active scanout the HVS and PV work in lockstep wrt. HVS in vc4_crtc_get_scanout_position()
144 * fifo, the HVS will immediately refill it, therefore in vc4_crtc_get_scanout_position()
145 * incrementing vpos. Therefore we choose HVS read position - in vc4_crtc_get_scanout_position()
[all …]
Dvc4_kms.c310 struct vc4_hvs *hvs = vc4->hvs; in vc4_atomic_complete_commit() local
325 if (vc4->hvs->hvs5) in vc4_atomic_complete_commit()
326 clk_set_min_rate(hvs->core_clk, 500000000); in vc4_atomic_complete_commit()
336 if (vc4->hvs->hvs5) in vc4_atomic_complete_commit()
355 if (vc4->hvs->hvs5) in vc4_atomic_complete_commit()
356 clk_set_min_rate(hvs->core_clk, 0); in vc4_atomic_complete_commit()
630 /* HVS clock is supposed to run @ 250Mhz, let's take a margin and in vc4_load_tracker_atomic_check()
749 * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
817 * routed to 1, 2 or 3 HVS FIFOs, and we need to set in vc4_pv_muxing_atomic_check()
819 * the HVS accordingly. in vc4_pv_muxing_atomic_check()
Dvc4_drv.h77 struct vc4_hvs *hvs; member
194 * demanding in term of memory or HVS bandwidth which is hard to guess
332 /* Memory manager for the LBM memory used by HVS scaling. */
340 /* HVS version 5 flag, therefore requires updated dlist structures */
413 /* Load of this plane on the HVS block. The load is expressed in HVS
461 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */
464 /* Which output of the HVS this pixelvalve sources from. */
549 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
550 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
Dvc4_regs.h221 /* Global register for clock gating the HVS */
394 /* Last pixel in the COB (display FIFO memory) allocated to this HVS
400 /* First pixel in the COB (display FIFO memory) allocated to this HVS
479 /* Slave addresses for DMAing from HVS composition output to other
755 /* HVS display list information. */
Dvc4_drv.c250 { .compatible = "brcm,bcm2711-hvs" },
251 { .compatible = "brcm,bcm2835-hvs" },
/kernel/linux/linux-6.6/net/vmw_vsock/
Dhyperv_transport.c251 struct hvsock *hvs = vsk->trans; in hvs_channel_cb() local
252 struct vmbus_channel *chan = hvs->chan; in hvs_channel_cb()
303 struct hvsock *hvs = NULL; in hvs_open_connection() local
353 hvs = vsock_sk(sk)->trans; in hvs_open_connection()
354 hvs->chan = chan; in hvs_open_connection()
393 hvs->chan = NULL; in hvs_open_connection()
444 struct hvsock *hvs; in hvs_sock_init() local
447 hvs = kzalloc(sizeof(*hvs), GFP_KERNEL); in hvs_sock_init()
448 if (!hvs) in hvs_sock_init()
451 vsk->trans = hvs; in hvs_sock_init()
[all …]
/kernel/linux/linux-5.10/net/vmw_vsock/
Dhyperv_transport.c242 struct hvsock *hvs = vsk->trans; in hvs_channel_cb() local
243 struct vmbus_channel *chan = hvs->chan; in hvs_channel_cb()
294 struct hvsock *hvs = NULL; in hvs_open_connection() local
344 hvs = vsock_sk(sk)->trans; in hvs_open_connection()
345 hvs->chan = chan; in hvs_open_connection()
382 hvs->chan = NULL; in hvs_open_connection()
433 struct hvsock *hvs; in hvs_sock_init() local
436 hvs = kzalloc(sizeof(*hvs), GFP_KERNEL); in hvs_sock_init()
437 if (!hvs) in hvs_sock_init()
440 vsk->trans = hvs; in hvs_sock_init()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/
Dbrcm,bcm2835-hvs.yaml4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-hvs.yaml#
15 - brcm,bcm2711-hvs
16 - brcm,bcm2835-hvs
39 const: brcm,bcm2711-hvs
47 hvs@7e400000 {
48 compatible = "brcm,bcm2835-hvs";
Dbrcm,bcm2835-vc4.yaml14 with HDMI output and the HVS (Hardware Video Scaler) for compositing
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/
Dbrcm,bcm2835-hvs.yaml4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-hvs.yaml#
15 - brcm,bcm2711-hvs
16 - brcm,bcm2835-hvs
39 const: brcm,bcm2711-hvs"
47 hvs@7e400000 {
48 compatible = "brcm,bcm2835-hvs";
Dbrcm,bcm2835-vc4.yaml14 with HDMI output and the HVS (Hardware Video Scaler) for compositing
/kernel/linux/linux-6.6/Documentation/gpu/
Dvc4.rst21 HVS section in Display Hardware Handling
25 :doc: VC4 HVS module.
27 HVS planes
73 * The HVS to PixelValve dynamic FIFO assignment, for the BCM2835-7
/kernel/linux/linux-5.10/Documentation/gpu/
Dvc4.rst21 HVS section in Display Hardware Handling
25 :doc: VC4 HVS module.
27 HVS planes
/kernel/linux/linux-6.6/drivers/gpu/drm/vc4/tests/
Dvc4_mock.c183 vc4->hvs = __vc4_hvs_alloc(vc4, NULL); in __mock_device()
184 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, vc4->hvs); in __mock_device()
/kernel/linux/linux-5.10/tools/testing/selftests/net/
Dtest_vxlan_under_vrf.sh7 # two for the HVs, two for the VMs.
88 # Check connectivity between HVs by pinging hv-2 from hv-1
/kernel/linux/linux-6.6/tools/testing/selftests/net/
Dtest_vxlan_under_vrf.sh7 # two for the HVs, two for the VMs.
88 # Check connectivity between HVs by pinging hv-2 from hv-1
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm2711-rpi.dtsi52 &hvs {

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