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/arkcompiler/runtime_core/static_core/compiler/optimizer/ir_builder/
Dinst_templates.yaml18 % raise "Wrong binop instruction" unless opc
20 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
25 auto inst_save_state = CreateSaveState(Opcode::SaveState, GetPc(instruction->GetAddress()));
26 …auto inst_check = graph_->CreateInstZeroCheck(<%= get_type(inst.dtype) %>, GetPc(instruction->GetA…
29 …inst_check->SetInput(0, FindOrCreate32BitConstant(instruction->GetImm<<%= inst.get_format %>, 0>()…
35 inst_check->SetInput(0, GetDefinition(instruction->GetVReg<<%=inst.get_format%>, 1>()));
41 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
44 inst->SetInput(0, GetDefinition(instruction->GetVReg<<%=inst.get_format%>, 0>()));
45 UpdateDefinition(instruction->GetVReg<<%=inst.get_format%>, 0>(), inst);
51 UpdateDefinition(instruction->GetVReg<<%=inst.get_format%>, 0>(), inst);
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/arkcompiler/runtime_core/static_core/libllvmbackend/transforms/passes/
Dgep_propagation.h27 class Instruction; variable
43 …sing SelectorSplitMap = llvm::DenseMap<llvm::Instruction *, std::pair<llvm::Instruction *, llvm::I…
45 void AddToVector(llvm::Instruction *inst, llvm::SmallVector<llvm::Instruction *> *toExpand,
46 llvm::SmallVector<llvm::Instruction *> *selectors);
50 …void SplitGepSelectors(llvm::Function *function, llvm::SmallVector<llvm::Instruction *> *selectors,
51 llvm::DenseMap<llvm::Instruction *, llvm::Instruction *> *sgeps);
53 … std::pair<llvm::Value *, llvm::Value *> GenerateInput(llvm::Value *input, llvm::Instruction *inst,
54 … llvm::Instruction *inPoint, const SelectorSplitMap &mapping);
56 void GenerateSelectorInputs(llvm::Instruction *inst, const SelectorSplitMap &mapping);
62 llvm::Value *GetConstantInput(llvm::Instruction *inst);
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Dgep_propagation.cpp41 using llvm::Instruction;
64 void GepPropagation::AddToVector(Instruction *inst, SmallVector<Instruction *> *toExpand, in AddToVector()
65 SmallVector<Instruction *> *selectors) in AddToVector()
69 case Instruction::GetElementPtr: in AddToVector()
75 case Instruction::PtrToInt: in AddToVector()
76 case Instruction::AddrSpaceCast: in AddToVector()
81 case Instruction::Select: in AddToVector()
82 case Instruction::PHI: in AddToVector()
95 SmallVector<Instruction *> toExpand; in Propagate()
96 SmallVector<Instruction *> selectors; in Propagate()
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Daarch64_fixup_sdiv.cpp32 bool AArch64FixupSDiv::ReplaceSelect(llvm::Instruction *selectInst) in ReplaceSelect()
34 auto cmp = llvm::cast<llvm::Instruction>(selectInst->getOperand(0U)); in ReplaceSelect()
38 // sub instruction may be replaced with value in ReplaceSelect()
39 auto sdivInst = llvm::cast<llvm::Instruction>(sdiv); in ReplaceSelect()
49 if (sub->uses().empty() && llvm::isa<llvm::Instruction>(sub)) { in ReplaceSelect()
50 auto subInst = llvm::cast<llvm::Instruction>(sub); in ReplaceSelect()
66 llvm::SmallVector<llvm::Instruction *> selectInsts; in run()
67 for (auto &instruction : basicBlock) { in run() local
68 if (instruction.hasMetadata(LLVMArkInterface::AARCH64_SDIV_INST)) { in run()
69 ASSERT(instruction.getOpcode() == llvm::Instruction::Select); in run()
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Dintrinsics_lowering.cpp52 std::unordered_map<llvm::Instruction *, llvm::Instruction *> instToReplaceWithInst; in run()
54 for (auto &instruction : block) { in run() local
55 auto llvmIntrinsicId = arkInterface_->GetLLVMIntrinsicId(&instruction); in run()
57 ASSERT(llvm::isa<llvm::CallInst>(&instruction)); in run()
58 … changed |= ReplaceWithLLVMIntrinsic(llvm::cast<llvm::CallInst>(&instruction), llvmIntrinsicId); in run()
61 auto intrinsicId = arkInterface_->GetIntrinsicId(&instruction); in run()
66 auto opcode = instruction.getOpcode(); in run()
67 if (opcode == llvm::Instruction::Call) { in run()
68 …changed |= HandleCall(llvm::cast<llvm::CallInst>(&instruction), intrinsicId, &instToReplaceWithIns… in run()
69 } else if (opcode == llvm::Instruction::FRem) { in run()
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Dintrinsics_lowering.h32 class Instruction; variable
56 … std::unordered_map<llvm::Instruction *, llvm::Instruction *> *instToReplaceWithInst);
58 … std::unordered_map<llvm::Instruction *, llvm::Instruction *> *instToReplaceWithInst);
60 bool HandleFRem(llvm::Instruction *inst, LLVMArkInterface::IntrinsicId intrinsicId,
61 … std::unordered_map<llvm::Instruction *, llvm::Instruction *> *instToReplaceWithInst);
Dgc_intrusion_check.h46 void CheckInstruction(const llvm::Function &func, const llvm::Instruction &inst);
48 …const llvm::Instruction *FindDefOrStatepoint(const llvm::Instruction *start, const llvm::Instructi…
50 …const llvm::Instruction *FindDefOrStatepointRecursive(const llvm::Instruction *start, const llvm::…
/arkcompiler/runtime_core/compiler/optimizer/ir/
Dinstructions.yaml16 Opcode of the instruction
19 Describes signature of the instruction. Properties of the operands are separated by '-' symbol.
26 …C++ base that represent this opcode. In far future if we managed to generate also instruction clas…
30 Properties of the instruction, such as: arithmetic, binop, throw, etc
33 Modes which the instruction can be used in
36 # Templates aim to reduce boilerplate in instruction description.
122 description: Phi instruction
128 description: Pseudo instruction that inserted by Register Allocator.
155 description: Pseudo instruction, inserted in the beginning of try-block.
163 …Pseudo instruction, which is inserted in the Catch handler basic block, and defines virtual regist…
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/arkcompiler/runtime_core/compiler/optimizer/ir_builder/
Dinst_templates.yaml18 % raise "Wrong binop instruction" unless opc
20 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
25 auto inst_save_state = CreateSaveState(Opcode::SaveState, GetPc(instruction->GetAddress()));
26 …auto inst_check = graph_->CreateInstZeroCheck(<%= get_type(inst.dtype) %>, GetPc(instruction->GetA…
29 …inst_check->SetInput(0, FindOrCreate32BitConstant(instruction->GetImm<<%= inst.get_format %>, 0>()…
37 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
45 … auto inst = graph_->CreateInstAdd(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddress()));
46 inst->SetInput(0, GetDefinition(instruction->GetVReg<<%=inst.get_format%>, 0>()));
48 … inst->SetInput(1, FindOrCreate32BitConstant(instruction->GetImm<<%=inst.get_format%>, 0>()));
50 inst->SetInput(1, FindOrCreateConstant(instruction->GetImm<<%=inst.get_format%>, 0>()));
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/arkcompiler/ets_frontend/testTs/instype/
Drecordthis-expected.txt2 (instruction order, type): (-2, 111), (-1, 106),
4 (instruction order, type): (-2, 111), (-1, 102),
6 (instruction order, type): (-2, 111), (-1, 103),
8 (instruction order, type): (-2, 111), (-1, 104),
10 (instruction order, type): (-2, 111), (-1, 105),
12 (instruction order, type): (-2, 111), (-1, 107), (16, 4),
14 (instruction order, type): (-2, 101), (-1, 108),
16 (instruction order, type): (-2, 111), (-1, 109),
18 (instruction order, type): (-2, 111), (-1, 110),
20 (instruction order, type): (-1, 112), (9, 1),
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Drecordimport-expected.txt2 (instruction order, type): (-1, 101),
4 (instruction order, type): (-2, 105),
6 (instruction order, type): (-1, 103),
8 (instruction order, type): (-1, 104),
10 (instruction order, type): (8, 101), (10, 1), (12, 103), (14, 104), (16, 1), (18, 1), (20, 1), (22,…
12 (instruction order, type): (5, 101), (8, 105), (19, 107), (22, 102), (25, 103), (31, 104), (37, 106…
Drecordexport-expected.txt2 (instruction order, type): (-1, 101),
4 (instruction order, type): (-2, 105),
6 (instruction order, type): (-1, 103),
8 (instruction order, type): (-1, 104),
10 (instruction order, type): (8, 101), (10, 1), (12, 103), (14, 104), (16, 1), (18, 1), (20, 1), (22,…
/arkcompiler/runtime_core/compiler/docs/
Dir_builder.md18 - some instructions don't specify its type, f.e. `mov` instruction may produce int32 as well as flo…
22 - if constant is `0` and it is used in instruction that expects object(f.e. `mov.obj`), we need to …
23 constant instruction `NullPtr` to handle this situation.
53 4. Get next bytecode instruction from the current basic block.
54 5. Build the Panda IR instruction from the bytecode instruction:
58 6. If instruction is a terminator, goto 1, else goto 4.
60 `Virtual register map` is a map, where key is virtual register, value is an IR instruction that cur…
66 …or all constants that are used in instructions with different types, split constant instruction and
99 # Next instruction starts new basic block
125 Example of the case for the `ADD` bytecode instruction in autogenerated `BuildInstruction` function.
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Dvn_doc.md5 Value numbering sets special numbers(`vn`) to all instructions. If two instruction has equal VN, so…
6 At the case we move users from second instruction to first instructions(first instruction is domina…
19 We pass through all instructions in PRO order. If the instruction has attribute NO_Cse, we set next…
20 For other instructions we save information: opcode, type, `vn` of instruction inputs, advanced prop…
24 …a. If some equivalent instruction dominates current instruction, we move users from current instru…
25 …e current instruction, we insert the instruction in the equivalent instructions vector, and also g…
26 …weren't found, we set next `vn` to the current instruction field and add information about the ins…
/arkcompiler/runtime_core/static_core/compiler/docs/
Dir_builder.md18 - some instructions don't specify its type, f.e. `mov` instruction may produce int32 as well as flo…
22 - if constant is `0` and it is used in instruction that expects object(f.e. `mov.obj`), we need to …
23 constant instruction `NullPtr` to handle this situation.
53 4. Get next bytecode instruction from the current basic block.
54 5. Build the Panda IR instruction from the bytecode instruction:
58 6. If instruction is a terminator, goto 1, else goto 4.
60 `Virtual register map` is a map, where key is virtual register, value is an IR instruction that cur…
66 …or all constants that are used in instructions with different types, split constant instruction and
99 # Next instruction starts new basic block
125 Example of the case for the `ADD` bytecode instruction in autogenerated `BuildInstruction` function.
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Dbridges.md8 2. Fix `SaveStates` for `source` instruction **ONLY** on path from `source` instructions to `target…
14 We need to be sure that the `source` instruction dominates the `target` instruction.
17 …et` instruction to the `source` and we are looking for SS that need to be fixed. We always can do …
22 …tates` and, if it is required, `CreateBridgeInSS`. It inserts `source` instruction into `SaveState…
24 …eState inputs if it is not there. Delete object from the SaveState, if instruction does not domina…
26 …ng for search SaveState on path to `target`, which don't have `source` instruction in input. Retur…
30 …mpBridges`** write in your `std::ostream` all bridges which need add for this `source` instruction.
36 … be deleted or moved, but the pointer will not change. As a result, in instruction v10 we can use …
79 | to target instruction
Dmemory_barriers_doc.md19 There is instruction flag `MEM_BARRIER`. The flag is set to `true` for the instructions NewObject, …
20 The pass `OptimizeMemoryBarriers` try remove the flag(set false) from the instruction.
21 …s through all instructions in PRO order. If the instruction has flag `MEM_BARRIER` we add the inst…
22 If we visit an instruction that can pass an object to another thread(Store instruction, Call instru…
23 If the instruction has input from the `barriers_insts_`, we call function `MergeBarriers`.
24 The function set `false` for the flag `MEM_BARRIER`, exclude last instruction from the vector.
25 So we will only set the barrier in the last instruction before potentially passing the created obje…
Dvn_doc.md5 Value numbering sets special numbers(`vn`) to all instructions. If two instruction has equal VN, so…
6 At the case we move users from second instruction to first instructions(first instruction is domina…
19 We pass through all instructions in PRO order. If the instruction has attribute NO_Cse, we set next…
20 For other instructions we save information: opcode, type, `vn` of instruction inputs, advanced prop…
24 …a. If some equivalent instruction dominates current instruction, we move users from current instru…
25 …e current instruction, we insert the instruction in the equivalent instructions vector, and also g…
26 …weren't found, we set next `vn` to the current instruction field and add information about the ins…
/arkcompiler/runtime_core/docs/
Dir_format.md7 * Compiler overhead about 100000 native instructions per a bytecode instruction(standard for JIT co…
65 ## Instruction set
76 …le to do arm specific optimizations. For this, need to support ARMv8-M Instruction Set(only those …
81 In the first step, Panda bytecode is converted to high level instruction and architecturally indepe…
87 …f 'native' instructions(ARM) that are spent compiling a single 'guest' instruction(from Bytecode).…
178 **Inst** is a base class with main information about an instruction.
179 * Opcode(name) of the instruction
180 * pc(address) instruction in bytecode/file
181 * Type of instruction(bool, uint8, uint32, float, double e.t.c)
189 Class **FixedInputsInst** inherits from **Inst** for instruction with a fixed number of inputs(oper…
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/arkcompiler/runtime_core/tests/cts-generator/cts-template/
Djeqz.obj.yaml24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
26 instruction address.
44 description: Check 'jeqz.obj' instruction with invalid offset.
68 description: Check 'jeqz.obj' instruction with uninitialized accumulator.
84 description: Check 'jeqz.obj' instruction with invalid branch target.
132 … description: Check 'jeqz.obj' instruction with prohibited branch target in PandaAssembly context.
209 … description: Check 'jeqz.obj' instruction with prohibited branch target in PandaAssembly context.
281 description: Check 'jeqz.obj' instruction with invalid accumulator value
389 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
391 instruction address.
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Djnez.obj.yaml24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
26 instruction address.
44 description: Check 'jnez.obj' instruction with invalid offset.
68 description: Check 'jnez.obj' instruction with uninitialized accumulator.
84 description: Check 'jnez.obj' instruction with invalid branch target.
132 … description: Check 'jnez.obj' instruction with prohibited branch target in PandaAssembly context.
209 … description: Check 'jnez.obj' instruction with prohibited branch target in PandaAssembly context.
281 description: Check 'jnez.obj' instruction with invalid accumulator value
389 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
391 instruction address.
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/arkcompiler/runtime_core/static_core/tests/cts-generator/cts-template/
Djeqz.obj.yaml20 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
22 instruction address.
39 description: Check 'jeqz.obj' instruction with invalid offset.
62 description: Check 'jeqz.obj' instruction with uninitialized accumulator.
77 description: Check 'jeqz.obj' instruction with invalid branch target.
119 description: Check 'jeqz.obj' instruction with prohibited branch target.
188 description: Check 'jeqz.obj' instruction with invalid accumulator value
295 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
297 instruction address.
298 description: Check 'jeqz.obj' instruction with valid null value.
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Djnez.obj.yaml20 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
22 instruction address.
39 description: Check 'jnez.obj' instruction with invalid offset.
62 description: Check 'jnez.obj' instruction with uninitialized accumulator.
77 description: Check 'jnez.obj' instruction with invalid branch target.
119 description: Check 'jnez.obj' instruction with prohibited branch target.
188 description: Check 'jnez.obj' instruction with invalid accumulator value
295 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
297 instruction address.
298 description: Check 'jnez.obj' instruction with valid null value.
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/arkcompiler/runtime_core/static_core/docs/
Dir_format.md7 * Compiler overhead about 100000 native instructions per a bytecode instruction(standard for JIT co…
74 ## Instruction set
85 …le to do arm specific optimizations. For this, need to support ARMv8-M Instruction Set(only those …
90 In the first step, Panda bytecode is converted to high level instruction and architecturally indepe…
96 …f 'native' instructions(ARM) that are spent compiling a single 'guest' instruction(from Bytecode).…
187 **Inst** is a base class with main information about an instruction.
188 * Opcode(name) of the instruction
189 * pc(address) instruction in bytecode/file
190 * Type of instruction(bool, uint8, uint32, float, double e.t.c)
198 Class **FixedInputsInst** inherits from **Inst** for instruction with a fixed number of inputs(oper…
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/arkcompiler/runtime_core/bytecode_optimizer/
Dbytecode_optimizer_isapi.rb16 Instruction.class_eval do
48 @instruction_hash = Hash.new { |_, key| raise "No instruction with '#{key}' mnemonic" }
100 Leaf = Struct.new(:instruction, :args) do
104 if instruction.acc_read?
105 res << do_lda(instruction)
108 res << "enc->result_.emplace_back(pandasm::Create_#{instruction.asm_token}(\n"
111 if instruction.acc_write?
112 res << do_sta(instruction)
119 reg = instruction.operands.select(&:reg?).first
180 # Type/cc cases for instruction selection
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