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/arkcompiler/runtime_core/static_core/tests/verifier-tests/
Dbug_2107_2.pa1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 #---
17 #- title: Integer truncations and extensions.
19 # Truncations discard all but N lowest-order bits, where N is the bit size of destination
24 # - x_none
26 # - sig: i64toi32
27 # acc: inout:i64->i32
29 # - op_none
31 # - acc_type
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/arkcompiler/runtime_core/tests/verifier-tests/
Dbug_2107_2.pa1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 #---
17 #- title: Integer truncations and extensions.
19 # Truncations discard all but N lowest-order bits, where N is the bit size of destination
24 # - x_none
26 # - sig: i64toi32
27 # acc: inout:i64->i32
29 # - op_none
31 # - acc_type
[all …]
/arkcompiler/runtime_core/libpandafile/
Dpanda_cache.h2 * Copyright (c) 2021-2022 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
34 // NOLINTNEXTLINE(cppcoreguidelines-special-member-functions, hicpp-special-member-functions)
71 // lowest one or two bits is very likely same between different fields in GetFieldIndex()
85 // Atomic with acquire order reason: fixes a data race with method_cache_ in GetMethodFromCache()
86 auto pair = pair_ptr->load(std::memory_order_acquire); in GetMethodFromCache()
103 // Atomic with release order reason: fixes a data race with method_cache_ in SetMethodCache()
104 pair_ptr->store(pair, std::memory_order_release); in SetMethodCache()
112 // Atomic with acquire order reason: fixes a data race with field_cache_ in GetFieldFromCache()
113 auto pair = pair_ptr->load(std::memory_order_acquire); in GetFieldFromCache()
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/arkcompiler/runtime_core/tests/cts-generator/cts-template/
Di64toi32.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 - file-name: "i64toi32"
21 … Truncations discard all but N lowest-order bits, where N is the bit size of destination type.
23 - x_none
25 - file-name: "op_none"
28 - sig: i64toi32
29 acc: inout:i64->i32
32 code-template: |
46 - values:
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Dcall.virt.short.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
13 ---
15 - name: PandaAssembly
18 - name: r_A
25 - name: r_R
38 - name: r_RJ
51 - name: NPE
54 - name: j_NPE
57 - name: AME
[all …]
/arkcompiler/runtime_core/static_core/tests/cts-generator/cts-template/
Di64toi32.yaml1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 - file-name: "i64toi32"
21 … Truncations discard all but N lowest-order bits, where N is the bit size of destination type.
23 - x_none
25 - file-name: "op_none"
28 - sig: i64toi32
29 acc: inout:i64->i32
32 code-template: |
46 - values:
[all …]
Dcall.virt.short.yaml1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
13 ---
15 - name: r_A
21 - name: r_R
34 - name: NPE
37 - name: AME
42 - file-name: call.virt.short
45 - sig: call.virt.short method_id, v1:in:top, v2:in:top
56 constant-pool based on object reference using language-specific semantics.
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/arkcompiler/runtime_core/static_core/libpandafile/
Dpanda_cache.h2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
34 // NOLINTNEXTLINE(cppcoreguidelines-special-member-functions, hicpp-special-member-functions)
71 // lowest one or two bits is very likely same between different fields in GetFieldIndex()
88 // Atomic with acquire order reason: fixes a data race with method_cache_ in GetMethodFromCache()
89 auto pair = pairPtr->load(std::memory_order_acquire); in GetMethodFromCache()
110 // Atomic with release order reason: fixes a data race with method_cache_ in SetMethodCache()
111 pairPtr->store(pair, std::memory_order_release); in SetMethodCache()
123 // Atomic with acquire order reason: fixes a data race with field_cache_ in GetFieldFromCache()
124 auto pair = pairPtr->load(std::memory_order_acquire); in GetFieldFromCache()
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/arkcompiler/runtime_core/static_core/compiler/docs/
Dmemory_coalescing_doc.md11 | ------ | ------ | ------|
19 * Reverse Post Order (RPO)
27 `AArch64` has `32`-bit and `64`-bit versions of coalescing operations – `ldp` and `stp`. As a resul…
43 | --- | --- |
49 | --- | --- |
50 …-> (v37)` <br> `61.i64 LoadArrayI v2, 0x1 -> (v43)` | `62.i64 LoadArrayPairI v2, 0x0 -> (v63, …
58 …implemented for array accesses. We process instructions of basic block in order. To find accesses …
71 3) Iterate candidates in backward order
79 1) find the lowest position the candidate can be sunk
81 …3) The place can be any between highest and lowest position. If the intersection is empty, coalesc…
[all …]
/arkcompiler/runtime_core/platforms/unix/libpandabase/futex/
Dfmutex.h2 * Copyright (c) 2021-2022 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
49 …D thread::ThreadId // NOLINT(cppcoreguidelines-macro-usage)
50 …ENT_THREAD os::thread::GetCurrentThreadId() // NOLINT(cppcoreguidelines-macro-usage)
51 …ype) std::atomic<type> // NOLINT(cppcoreguidelines-macro-usage)
52 …NT ATOMIC(int) // NOLINT(cppcoreguidelines-macro-usage)
53 #define ATOMIC_STORE(addr, val, mem) (addr)->store(val, std::mem) // NOLINT(cppcoreguideli…
54 #define ATOMIC_LOAD(addr, mem) (addr)->load(std::mem) // NOLINT(cppcoreguideli…
55 …efine ATOMIC_FETCH_ADD(addr, val, mem) (addr)->fetch_add(val, std::mem) // NOLINT(cppcoreguidelin…
56 …efine ATOMIC_FETCH_SUB(addr, val, mem) (addr)->fetch_sub(val, std::mem) // NOLINT(cppcoreguidelin…
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/arkcompiler/runtime_core/static_core/platforms/unix/libpandabase/futex/
Dfmutex.h2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
48 …D ark::os::thread::ThreadId // NOLINT(cppcoreguidelines-macro-usage)
49 …ENT_THREAD ark::os::thread::GetCurrentThreadId() // NOLINT(cppcoreguidelines-macro-usage)
50 …ype) std::atomic<type> // NOLINT(cppcoreguidelines-macro-usage)
51 …NT ATOMIC(int) // NOLINT(cppcoreguidelines-macro-usage)
52 #define ATOMIC_STORE(addr, val, mem) (addr)->store(val, std::mem) // NOLINT(cppcoreguideli…
53 #define ATOMIC_LOAD(addr, mem) (addr)->load(std::mem) // NOLINT(cppcoreguideli…
54 …efine ATOMIC_FETCH_ADD(addr, val, mem) (addr)->fetch_add(val, std::mem) // NOLINT(cppcoreguidelin…
55 …efine ATOMIC_FETCH_SUB(addr, val, mem) (addr)->fetch_sub(val, std::mem) // NOLINT(cppcoreguidelin…
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/
Dschedule_heuristic.h7 * http://www.apache.org/licenses/LICENSE-2.0
22 // - positive: node1 has higher priority
23 // - negative: node2 has higher priority
24 // - zero: node1 == node2
33 return static_cast<int>(node1.GetDelay() - node2.GetDelay()); in operator()
39 // byte, prefer lowest offset.
41 // (2) If one insn is store and the other is not memory operation, prefer non-memory-insn scheduled…
42 …e insn is load and the other is not memory operation, prefer load scheduled before non-memory-insn.
52 if (insn1->IsMemAccess() && insn2->IsMemAccess()) { in operator()
53 auto *memOpnd1 = static_cast<MemOperand *>(insn1->GetMemOpnd()); in operator()
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/
Dreg_alloc_lsra.cpp7 * http://www.apache.org/licenses/LICENSE-2.0
25 /* Here, kLoopWeight is a fine-tuned empirical parameter */
31 * BFS BB ordering is used to order the instructions. The live intervals are vased on
32 * this instruction order. All vreg defines should come before an use, else a warning is
34 * Live interval is traversed in order from lower instruction order to higher order.
76 LogInfo::MapleLogger() << "(assigned " << regType << (li.GetAssignedReg() - base) << ")"; in PrintLiveRanges()
97 LogInfo::MapleLogger() << "func: " << cgFunc->GetName() << "\n"; in PrintAllLiveRanges()
99 if (li == nullptr || li->GetRegNO() == 0) { in PrintAllLiveRanges()
102 LogInfo::MapleLogger() << "vreg" << li->GetRegNO() << ": "; in PrintAllLiveRanges()
103 if (li->GetSplitParent() != nullptr) { in PrintAllLiveRanges()
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Dlist_scheduler.cpp7 * http://www.apache.org/licenses/LICENSE-2.0
31 … LogInfo::MapleLogger() << "## --- schedule bb_" << curCDGNode->GetBB()->GetId() << " ---\n\n"; in DoListScheduling()
44 while (scheduledNodeNum < curCDGNode->GetInsnNum()) { in DoListScheduling()
76 // Sort the readyList by priority from highest to lowest in DoListScheduling()
88 … LogInfo::MapleLogger() << " >> Select node: insn_" << schedNode->GetInsn()->GetId() << "\n\n"; in DoListScheduling()
91 if (schedNode->GetInsn()->GetBB()->GetId() == curCDGNode->GetBB()->GetId()) { in DoListScheduling()
105 mad = Globals::GetInstance()->GetMAD(); in Init()
110 mad->ReleaseAllUnits(); in Init()
115 MapleVector<DepNode *> &candidates = commonSchedInfo->GetCandidates(); in Init()
118 depNode->SetEStart(0); in Init()
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/mpl2mpl/src/
Dclass_hierarchy.cpp7 * http://www.apache.org/licenses/LICENSE-2.0
29 // B. Fill class method info. Connect superclass<->subclass and
30 // interface->implementation edges.
36 // F. Based on Topological Sort Order, for each virtual method in a class,
51 superKlasses(alloc->Adapter()), in Klass()
52 subKlasses(alloc->Adapter()), in Klass()
53 implKlasses(alloc->Adapter()), in Klass()
54 implInterfaces(alloc->Adapter()), in Klass()
55 methods(alloc->Adapter()), in Klass()
56 strIdx2Method(alloc->Adapter()), in Klass()
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/arkcompiler/runtime_core/static_core/plugins/ets/doc/spec/
D7_expressions.rst2 Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 http://www.apache.org/licenses/LICENSE-2.0
33 .. code-block:: abnf
80 .. code-block:: abnf
90 - A class or an interface that are to handle static members;
91 - ``Super`` that is to access shadowed fields or constructors declared in the
93 - *primaryExpression* that is to refer to an instance variable of a class
98 "this?." is handled as a :index:`compile-time error`.
101 is handled as a :index:`compile-time error`.
103 .. code-block:: abnf
[all …]
D3_types.rst2 Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 http://www.apache.org/licenses/LICENSE-2.0
23 Type classification as accepted in |LANG| is discussed below---along
45 *user-defined types*.
46 All *user-defined types* must always have complete type definitions
58 user-defined type
74 - Basic numeric value type: ``number``
76 - High-performance value types:
78 - Numeric types: ``byte``, ``short``, ``int``, ``long``, ``float``, and
81 - Character type: ``char``;
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/arkcompiler/runtime_core/static_core/plugins/ets/compiler/optimizer/optimizations/interop_js/
Dinterop_intrinsic_optimization.cpp2 * Copyright (c) 2023-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
26 return inst->IsCall() && !static_cast<CallInst *>(inst)->IsInlined(); in IsForbiddenInst()
31 return inst->IsIntrinsic() && inst->CastToIntrinsic()->GetIntrinsicId() == in IsScopeStart()
37 return inst->IsIntrinsic() && inst->CastToIntrinsic()->GetIntrinsicId() == in IsScopeEnd()
67 if (!inst->IsIntrinsic()) { in IsConvertIntrinsic()
70 auto id = inst->CastToIntrinsic()->GetIntrinsicId(); in IsConvertIntrinsic()
76 if (!inst->IsIntrinsic()) { in IsInteropIntrinsic()
79 auto id = inst->CastToIntrinsic()->GetIntrinsicId(); in IsInteropIntrinsic()
85 if (!inst->IsIntrinsic()) { in CanCreateNewScopeObject()
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/arkcompiler/runtime_core/static_core/isa/
Disa.yaml1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
14 ---
17 - name: General design
21 - name: Registers
31 - name: Accumulator
40 register-to-register moves.
42 - name: Calling sequence
48 …On return, callee frame is destroyed. If function return value is non-void, it is passed to caller…
52 - name: Supported primitive types
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/arkcompiler/runtime_core/static_core/compiler/optimizer/ir/
Dinst.h2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
28 #include "ir-dyn-base-types.h"
58 * N.B. BranchElimination and Peephole rely on the order of these codes. Change carefully.
64 // Signed integers and floating-point numbers.
129 INVALID = -1,
130 // NOLINTBEGIN(readability-identifier-naming)
131 // NOLINTNEXTLINE(cppcoreguidelines-macro-usage)
136 // NOLINTEND(readability-identifier-naming)
142 // NOLINTNEXTLINE(cppcoreguidelines-macro-usage)
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/aarch64/
Daarch64_cgfunc.cpp7 * http://www.apache.org/licenses/LICENSE-2.0
105 "unknown Memory Order"); in PickLdStInsn()
109 "unknown Memory Order"); in PickLdStInsn()
112 /* __builtin_ffs(x) returns: 0 -> 0, 1 -> 1, 2 -> 2, 4 -> 3, 8 -> 4 */ in PickLdStInsn()
125 DEBUG_ASSERT((bitSize & (bitSize - 1)) == 0, "bitlen error"); in PickLdStInsn()
128 /* __builtin_ffs(x) returns: 8 -> 4, 16 -> 5, 32 -> 6, 64 -> 7 */ in PickLdStInsn()
132 uint32 size = static_cast<uint32>(__builtin_ffs(static_cast<int32>(bitSize))) - k4BitSize; in PickLdStInsn()
143 /* __builtin_ffs(x) returns: 32 -> 6, 64 -> 7, 128 -> 8 */ in PickLdStInsn()
144 uint32 size = static_cast<uint32>(__builtin_ffs(static_cast<int32>(bitSize))) - k6BitSize; in PickLdStInsn()
155 if (dest->GetOpCode() == OP_regread) { in IsBlkassignForPush()
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/arkcompiler/ets_frontend/legacy_bin/api8/src/
Dindex.js2 …-from/index.js":e=>{var t=Object.prototype.toString,r="undefined"!=typeof Buffer&&"function"==type… property