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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra114-mipi.txt1 NVIDIA Tegra MIPI pad calibration controller
4 - compatible: "nvidia,tegra<chip>-mipi"
5 - reg: Physical base address and length of the controller's registers.
6 - clocks: Must contain an entry for each entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must include the following entries:
9 - mipi-cal
10 - #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads
13 User nodes need to contain an nvidia,mipi-calibrate property that has a
19 mipi: mipi@700e3000 {
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Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra114-mipi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra MIPI pad calibration controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^mipi@[0-9a-f]+$"
19 - nvidia,tegra114-mipi
20 - nvidia,tegra210-mipi
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Dnvidia,tegra20-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
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/kernel/linux/linux-5.10/drivers/gpu/host1x/
Dmipi.c131 struct tegra_mipi *mipi; member
136 static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi, in tegra_mipi_readl() argument
139 return readl(mipi->regs + (offset << 2)); in tegra_mipi_readl()
142 static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value, in tegra_mipi_writel() argument
145 writel(value, mipi->regs + (offset << 2)); in tegra_mipi_writel()
148 static int tegra_mipi_power_up(struct tegra_mipi *mipi) in tegra_mipi_power_up() argument
153 err = clk_enable(mipi->clk); in tegra_mipi_power_up()
157 value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0); in tegra_mipi_power_up()
160 if (mipi->soc->needs_vclamp_ref) in tegra_mipi_power_up()
163 tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0); in tegra_mipi_power_up()
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/kernel/linux/linux-6.6/drivers/gpu/host1x/
Dmipi.c131 struct tegra_mipi *mipi; member
136 static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi, in tegra_mipi_readl() argument
139 return readl(mipi->regs + (offset << 2)); in tegra_mipi_readl()
142 static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value, in tegra_mipi_writel() argument
145 writel(value, mipi->regs + (offset << 2)); in tegra_mipi_writel()
148 static int tegra_mipi_power_up(struct tegra_mipi *mipi) in tegra_mipi_power_up() argument
153 err = clk_enable(mipi->clk); in tegra_mipi_power_up()
157 value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0); in tegra_mipi_power_up()
160 if (mipi->soc->needs_vclamp_ref) in tegra_mipi_power_up()
163 tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0); in tegra_mipi_power_up()
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
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/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
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/kernel/linux/linux-5.10/include/linux/phy/
Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
19 #include <linux/phy/phy-dp.h>
20 #include <linux/phy/phy-mipi-dphy.h>
48 * union phy_configure_opts - Opaque generic phy configuration
61 * struct phy_ops - set of function pointers for performing phy operations
68 * @calibrate: calibrate the phy
110 int (*calibrate)(struct phy *phy); member
116 * struct phy_attrs - represents phy attributes
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/kernel/linux/linux-6.6/include/linux/phy/
Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
19 #include <linux/phy/phy-dp.h>
20 #include <linux/phy/phy-lvds.h>
21 #include <linux/phy/phy-mipi-dphy.h>
55 * union phy_configure_opts - Opaque generic phy configuration
71 * struct phy_ops - set of function pointers for performing phy operations
80 * @calibrate: calibrate the phy
124 int (*calibrate)(struct phy *phy); member
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0031_linux_drivers_perf_phy_pinctrl_ptp_pwm.patch7 Change-Id: I50a0069a60f92f57dd6112f6a9700811be19e564
9 diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
11 --- a/drivers/perf/fsl_imx8_ddr_perf.c
13 @@ -5,6 +5,7 @@
21 @@ -14,12 +15,15 @@
37 @@ -28,9 +32,18 @@
56 @@ -40,32 +53,56 @@
80 -static const struct fsl_ddr_devtype_data imx8_devtype_data;
106 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
107 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
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/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/fw/
Dfile.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2008-2014, 2018-2021 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
55 IWL_UCODE_TLV_PAN = 7, /* deprecated -- only used in DVM */
56 IWL_UCODE_TLV_MEM_DESC = 7, /* replaces PAN in non-DVM */
117 /* TLVs 0x1000-0x2000 are for internal driver usage */
169 * enum iwl_ucode_tlv_flag - ucode API flags
205 * enum iwl_ucode_tlv_api - ucode api
296 * enum iwl_ucode_tlv_capa - ucode capabilities
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/kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/fw/
Dfile.h8 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
9 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
10 * Copyright(c) 2008 - 2014, 2018 - 2020 Intel Corporation
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
31 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
32 * Copyright(c) 2008 - 2014, 2018 - 2020 Intel Corporation
164 /* TLVs 0x1000-0x2000 are for internal driver usage */
216 * enum iwl_ucode_tlv_flag - ucode API flags
254 * enum iwl_ucode_tlv_api - ucode api
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