| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | samsung,mipi-video-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,mipi-video-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P/Exynos SoC MIPI CSIS/DSIM DPHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,s5pv210-mipi-video-phy compatible PHYs the second cell in the
16 PHY specifier identifies the PHY and its meaning is as follows::
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| D | mediatek,dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek MIPI Display Serial Interface (DSI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 description: The MIPI DSI PHY supports up to 4-lane output.
19 pattern: "^dsi-phy@[0-9a-f]+$"
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| D | mixel,mipi-dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel DSI PHY for i.MX8
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
17 The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
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| D | allwinner,sun6i-a31-mipi-dphy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI D-PHY Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - const: allwinner,sun50i-a100-mipi-dphy
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| D | rockchip-mipi-dphy-rx0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
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| D | amlogic,axg-mipi-dphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic AXG MIPI D-PHY
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,axg-mipi-dphy
24 clock-names:
26 - const: pclk
31 reset-names:
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| D | amlogic,meson-axg-mipi-pcie-analog.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic AXG shared MIPI/PCIE analog PHY
10 - Remi Pommarel <repk@triplefau.lt>
13 The Everything-Else Power Domains node should be the child of a syscon
16 - compatible: Should be the following:
17 "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"
24 const: amlogic,axg-mipi-pcie-analog-phy
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| /kernel/linux/linux-6.6/drivers/phy/mediatek/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the phy drivers.
6 obj-$(CONFIG_PHY_MTK_DP) += phy-mtk-dp.o
7 obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
8 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
9 obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
10 obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
12 phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
13 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
14 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8173.o
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | nxp,imx-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | rockchip-mipi-dphy-rx0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
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| D | samsung-phy.txt | 1 Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
14 In case of exynos5433 compatible PHY:
15 - samsung,pmu-syscon - phandle to the PMU system controller
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| D | allwinner,sun6i-a31-mipi-dphy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI D-PHY Controller Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - items:
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| D | amlogic,meson-axg-mipi-pcie-analog.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Amlogic AXG shared MIPI/PCIE analog PHY
10 - Remi Pommarel <repk@triplefau.lt>
14 const: amlogic,axg-mipi-pcie-analog-phy
19 "#phy-cells":
23 - compatible
24 - reg
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| D | mixel,mipi-dsi-phy.txt | 1 Mixel DSI PHY for i.MX8
3 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
4 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
8 - compatible: Must be:
9 - "fsl,imx8mq-mipi-dphy"
10 - clocks: Must contain an entry for each entry in clock-names.
11 - clock-names: Must contain the following entries:
12 - "phy_ref": phandle and specifier referring to the DPHY ref clock
13 - reg: the register range of the PHY controller
14 - #phy-cells: number of cells in PHY, as defined in
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| /kernel/linux/linux-6.6/drivers/phy/rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
32 tristate "Rockchip INNO HDMI PHY Driver"
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| /kernel/linux/linux-6.6/drivers/phy/amlogic/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Amlogic platforms
6 tristate "Meson8, Meson8b and Meson8m2 HDMI TX PHY driver"
16 tristate "Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY driver"
29 tristate "Meson GXL and GXM USB2 PHY drivers"
41 tristate "Meson G12A MIPI Analog DPHY driver"
48 Enable this to support the Meson MIPI Analog DPHY found in Meson G12A
53 tristate "Meson G12A USB2 PHY driver"
64 tristate "Meson G12A USB3+PCIE Combo PHY driver"
70 Enable this to support the Meson USB3 + PCIE Combo PHY found
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| D | phy-meson-axg-mipi-dphy.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Meson AXG MIPI DPHY driver
20 #include <linux/phy/phy.h>
23 /* [31] soft reset for the phy.
30 * [25] mipi dsi pll clock selection.
32 * [12] mipi HSbyteclk enable.
33 * [11] mipi divider clk selection.
34 * 1: select the mipi DDRCLKHS from clock divider.
36 * [10] mipi clock divider control.
38 * [9] mipi divider output enable.
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| /kernel/linux/linux-5.10/drivers/phy/amlogic/ |
| D | phy-meson-axg-mipi-pcie-analog.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic AXG MIPI + PCIE analog PHY driver
8 #include <linux/phy/phy.h>
11 #include <dt-bindings/phy/phy.h>
34 #define HHI_MIPI_CNTL2_CH_EN(n) BIT(15 - (n))
38 struct phy *phy; member
50 static int phy_axg_mipi_pcie_analog_power_on(struct phy *phy) in phy_axg_mipi_pcie_analog_power_on() argument
52 struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy); in phy_axg_mipi_pcie_analog_power_on()
54 /* MIPI not supported yet */ in phy_axg_mipi_pcie_analog_power_on()
55 if (priv->mode != PHY_TYPE_PCIE) in phy_axg_mipi_pcie_analog_power_on()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dsi.txt | 5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
9 - compatible: "mediatek,<chip>-dsi"
10 - the supported chips are mt2701, mt7623, mt8173 and mt8183.
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "engine", "digital", and "hs"
16 - phys: phandle link to the MIPI D-PHY controller.
17 - phy-names: must contain "dphy"
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/rockchip/ |
| D | rockchip,dw-mipi-dsi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - enum:
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3288-mipi-dsi
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | imx7-mipi-csi2.txt | 1 Freescale i.MX7 Mipi CSI2
5 --------------
7 This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
8 compatible with previous version of Samsung D-phy.
12 - compatible : "fsl,imx7-mipi-csi2";
13 - reg : base address and length of the register set for the device;
14 - interrupts : should contain MIPI CSIS interrupt;
15 - clocks : list of clock specifiers, see
16 Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
17 - clock-names : must contain "pclk", "wrap" and "phy" entries, matching
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/rockchip/ |
| D | dw_mipi_dsi_rockchip.txt | 1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: one of
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 - reg: Represent the physical address range of the controller.
12 - interrupts: Represent the controller's interrupt to the CPU(s).
13 - clocks, clock-names: Phandles to the controller's pll reference
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/ |
| D | samsung,mipi-dsim.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung MIPI DSIM bridge controller
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
15 Samsung MIPI DSIM bridge controller can be found it on Exynos
21 - enum:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_dsim.txt | 1 Exynos MIPI DSI Master
4 - compatible: value should be one of the following
5 "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6 "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7 "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
8 "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
9 "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
10 - reg: physical base address and length of the registers set for the device
11 - interrupts: should contain DSI interrupt
12 - clocks: list of clock specifiers, must contain an entry for each required
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| /kernel/linux/linux-5.10/drivers/phy/rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
32 tristate "Rockchip INNO HDMI PHY Driver"
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