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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,infracfg.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 The Mediatek infracfg controller provides various clocks and reset outputs
14 to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
15 and reset values in <dt-bindings/reset/mt*-reset.h> and
16 <dt-bindings/reset/mt*-resets.h>.
21 - items:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,infracfg.txt1 Mediatek infracfg controller
4 The Mediatek infracfg controller provides various clocks and reset
9 - compatible: Should be one of:
10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6765-infracfg", "syscon"
13 - "mediatek,mt6779-infracfg_ao", "syscon"
14 - "mediatek,mt6797-infracfg", "syscon"
15 - "mediatek,mt7622-infracfg", "syscon"
16 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
Dmt6795.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
10 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
11 #include <dt-bindings/memory/mt6795-larb-port.h>
12 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
13 #include <dt-bindings/power/mt6795-power.h>
14 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
18 interrupt-parent = <&sysirq>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt11 power/power-domain.yaml. It provides the power domains defined in
12 - include/dt-bindings/power/mt8173-power.h
13 - include/dt-bindings/power/mt6797-power.h
14 - include/dt-bindings/power/mt6765-power.h
15 - include/dt-bindings/power/mt2701-power.h
16 - include/dt-bindings/power/mt2712-power.h
17 - include/dt-bindings/power/mt7622-power.h
20 - compatible: Should be one of:
21 - "mediatek,mt2701-scpsys"
22 - "mediatek,mt2712-scpsys"
[all …]
Dpwrap.txt20 - compatible:
21 "mediatek,mt2701-pwrap" for MT2701/7623 SoCs
22 "mediatek,mt6765-pwrap" for MT6765 SoCs
23 "mediatek,mt6779-pwrap" for MT6779 SoCs
24 "mediatek,mt6797-pwrap" for MT6797 SoCs
25 "mediatek,mt7622-pwrap" for MT7622 SoCs
26 "mediatek,mt8135-pwrap" for MT8135 SoCs
27 "mediatek,mt8173-pwrap" for MT8173 SoCs
28 "mediatek,mt8183-pwrap" for MT8183 SoCs
29 "mediatek,mt8516-pwrap" for MT8516 SoCs
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt11 power/power-domain.yaml. It provides the power domains defined in
12 - include/dt-bindings/power/mt8173-power.h
13 - include/dt-bindings/power/mt6797-power.h
14 - include/dt-bindings/power/mt6765-power.h
15 - include/dt-bindings/power/mt2701-power.h
16 - include/dt-bindings/power/mt2712-power.h
17 - include/dt-bindings/power/mt7622-power.h
20 - compatible: Should be one of:
21 - "mediatek,mt2701-scpsys"
22 - "mediatek,mt2712-scpsys"
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
35 +----------------+-------
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/
Dmediatek,power-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
17 IP cores belonging to a power domain should contain a 'power-domains'
22 pattern: '^power-controller(@[0-9a-f]+)?$'
26 - mediatek,mt6795-power-controller
27 - mediatek,mt8167-power-controller
[all …]
/kernel/linux/linux-6.6/drivers/clk/mediatek/
Dclk-mt8173-infracfg.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/mt8173-clk.h>
11 #include "clk-cpumux.h"
12 #include "clk-gate.h"
13 #include "clk-mtk.h"
74 { .compatible = "mediatek,mt8173-infracfg" },
88 infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); in clk_mt8173_infra_init_early()
95 CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg",
100 struct device_node *node = pdev->dev.of_node; in clk_mt8173_infracfg_probe()
103 r = mtk_clk_register_gates(&pdev->dev, node, infra_gates, in clk_mt8173_infracfg_probe()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
6 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
7 obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
8 obj-$(CONFIG_COMMON_CLK_MT6765_IMGSYS) += clk-mt6765-img.o
9 obj-$(CONFIG_COMMON_CLK_MT6765_MIPI0ASYS) += clk-mt6765-mipi0a.o
10 obj-$(CONFIG_COMMON_CLK_MT6765_MMSYS) += clk-mt6765-mm.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_VCODECSYS) += clk-mt6765-vcodec.o
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dmtk-afe-pcm.txt4 - compatible = "mediatek,mt8173-afe-pcm";
5 - reg: register location and size
6 - interrupts: Should contain AFE interrupt
7 - clock-names: should have these clock names:
21 afe: mt8173-afe-pcm@11220000 {
22 compatible = "mediatek,mt8173-afe-pcm";
25 clocks = <&infracfg INFRA_AUDIO>,
35 clock-names = "infra_sys_audio_clk",
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dmtk-afe-pcm.txt4 - compatible = "mediatek,mt8173-afe-pcm";
5 - reg: register location and size
6 - interrupts: Should contain AFE interrupt
7 - clock-names: should have these clock names:
21 afe: mt8173-afe-pcm@11220000 {
22 compatible = "mediatek,mt8173-afe-pcm";
25 clocks = <&infracfg INFRA_AUDIO>,
35 clock-names = "infra_sys_audio_clk",
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,cec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
19 - mediatek,mt7623-cec
20 - mediatek,mt8167-cec
21 - mediatek,mt8173-cec
33 - compatible
34 - reg
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/
Dmediatek,gce-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Houlong Wei <houlong.wei@mediatek.com>
20 - enum:
21 - mediatek,mt6779-gce
22 - mediatek,mt8173-gce
23 - mediatek,mt8183-gce
24 - mediatek,mt8186-gce
[all …]
/kernel/linux/linux-5.10/drivers/soc/mediatek/
Dmtk-scpsys.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/soc/mediatek/infracfg.h>
16 #include <dt-bindings/power/mt2701-power.h>
17 #include <dt-bindings/power/mt2712-power.h>
18 #include <dt-bindings/power/mt6797-power.h>
19 #include <dt-bindings/power/mt7622-power.h>
20 #include <dt-bindings/power/mt7623a-power.h>
21 #include <dt-bindings/power/mt8173-power.h>
28 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
37 #define SPM_AUDIO_PWR_CON 0x029c /* MT8173, MT2712 */
[all …]
/kernel/linux/linux-6.6/drivers/pmdomain/mediatek/
Dmtk-scpsys.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/soc/mediatek/infracfg.h>
16 #include <dt-bindings/power/mt2701-power.h>
17 #include <dt-bindings/power/mt2712-power.h>
18 #include <dt-bindings/power/mt6797-power.h>
19 #include <dt-bindings/power/mt7622-power.h>
20 #include <dt-bindings/power/mt7623a-power.h>
21 #include <dt-bindings/power/mt8173-power.h>
28 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
37 #define SPM_AUDIO_PWR_CON 0x029c /* MT8173, MT2712 */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dmtk-gce.txt9 mailbox.txt for generic information about mailbox device-tree bindings.
12 - compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or
13 "mediatek,mt6779-gce".
14 - reg: Address range of the GCE unit
15 - interrupts: The interrupt signal from the GCE block
16 - clock: Clocks according to the common clock binding
17 - clock-names: Must be "gce" to stand for GCE clock
18 - #mbox-cells: Should be 2.
25 - mboxes: Client use mailbox to communicate with GCE, it should have this
28 - mediatek,gce-client-reg: Specify the sub-system id which is corresponding
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/
Dmediatek,mt2701-auxadc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/mediatek,mt2701-auxadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek AUXADC - ADC on Mediatek mobile SoC (mt65xx/mt81xx/mt27xx)
10 - Zhiyong Tao <zhiyong.tao@mediatek.com>
11 - Matthias Brugger <matthias.bgg@gmail.com>
18 directly via its own bus interface. See mediatek-thermal bindings
24 - enum:
25 - mediatek,mt2701-auxadc
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,hdmi.txt8 - compatible: Should be "mediatek,<chip>-hdmi".
9 - the supported chips are mt2701, mt7623 and mt8173
10 - reg: Physical base address and length of the controller's registers
11 - interrupts: The interrupt signal from the function block.
12 - clocks: device clocks
13 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
14 - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
15 - phys: phandle link to the HDMI PHY node.
16 See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
17 - phy-names: must contain "hdmi"
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.txt6 ARM Short-Descriptor translation table format for address translation.
14 +--------+
16 gals0-rx gals1-rx (Global Async Local Sync rx)
19 gals0-tx gals1-tx (Global Async Local Sync tx)
21 +--------+
25 +----------------+-------
27 | gals-rx There may be GALS in some larbs.
30 | gals-tx
36 +-----+-----+ +----+----+
53 smi-common and m4u, and additional GALS module between smi-larb and
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/mediatek/
Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
[all …]
Dmt7623.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
[all …]

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