| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.txt | 1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
[all …]
|
| D | imx219.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
15 I2C interface. The I2C address is fixed to 0x10 as per sensor data sheet.
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
[all …]
|
| D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
[all …]
|
| /kernel/linux/linux-5.10/include/linux/phy/ |
| D | phy-dp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
31 * lane 0, used for the transmissions on main link.
41 * to be used by particular lanes. One value per lane.
42 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
52 * used by particular lanes. One value per lane.
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
78 * Flag indicating, whether or not reconfigure lane count to
88 * and pre-emphasis to requested values. Only lanes specified
|
| /kernel/linux/linux-6.6/include/linux/phy/ |
| D | phy-dp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
31 * lane 0, used for the transmissions on main link.
41 * to be used by particular lanes. One value per lane.
42 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
52 * used by particular lanes. One value per lane.
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
78 * Flag indicating, whether or not reconfigure lane count to
88 * and pre-emphasis to requested values. Only lanes specified
|
| D | phy-lvds.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_lvds - LVDS configuration set
11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
16 * data lanes, starting from lane 0,
|
| /kernel/linux/linux-6.6/drivers/phy/freescale/ |
| D | phy-fsl-lynx-28g.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
14 /* General registers per SerDes block */
24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
26 /* Per PLL registers */
45 /* Per SerDes lane registers */
46 /* Lane a General Control Register */
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
55 /* Lane a Tx Reset Control Register */
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | video-interfaces.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | uncore-io.json | 12 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
27 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
123 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
129 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
140 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
151 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
162 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
173 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
184 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
195 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/ |
| D | phy-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/ |
| D | phy-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | uncore-io.json | 94 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
100 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
111 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
122 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
133 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
144 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
155 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
166 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
177 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
188 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
[all …]
|
| D | imx219.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
15 I2C interface. The I2C address is fixed to 0x10 as per sensor data sheet.
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
[all …]
|
| D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/tegra/ |
| D | dp.h | 1 /* SPDX-License-Identifier: MIT */
3 * Copyright (C) 2013-2019 NVIDIA Corporation.
18 * struct drm_dp_link_caps - DP link capabilities
61 * struct drm_dp_link_ops - DP link operations
80 * struct drm_dp_link_train_set - link training settings
81 * @voltage_swing: per-lane voltage swing
82 * @pre_emphasis: per-lane pre-emphasis
83 * @post_cursor: per-lane post-cursor
92 * struct drm_dp_link_train - link training state information
110 * struct drm_dp_link - DP link capabilities and configuration
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/tegra/ |
| D | dp.h | 1 /* SPDX-License-Identifier: MIT */
3 * Copyright (C) 2013-2019 NVIDIA Corporation.
18 * struct drm_dp_link_caps - DP link capabilities
61 * struct drm_dp_link_ops - DP link operations
80 * struct drm_dp_link_train_set - link training settings
81 * @voltage_swing: per-lane voltage swing
82 * @pre_emphasis: per-lane pre-emphasis
83 * @post_cursor: per-lane post-cursor
92 * struct drm_dp_link_train - link training state information
110 * struct drm_dp_link - DP link capabilities and configuration
|
| /kernel/linux/linux-6.6/net/atm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
9 ATM is a high-speed networking technology for Local Area Networks
18 Note that you need a set of user-space programs to actually make use
29 (LANE)" below.
42 tristate "LAN Emulation (LANE) support"
47 LANE client can also act as an proxy client bridging packets between
48 ELAN and Ethernet segments. You need LANE if you want to try MPOA.
51 tristate "Multi-Protocol Over ATM (MPOA) support"
54 Multi-Protocol Over ATM allows ATM edge devices such as routers,
69 bool "Per-VC IP filter kludge"
[all …]
|
| /kernel/linux/linux-5.10/net/atm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
9 ATM is a high-speed networking technology for Local Area Networks
18 Note that you need a set of user-space programs to actually make use
29 (LANE)" below.
42 tristate "LAN Emulation (LANE) support"
47 LANE client can also act as an proxy client bridging packets between
48 ELAN and Ethernet segments. You need LANE if you want to try MPOA.
51 tristate "Multi-Protocol Over ATM (MPOA) support"
54 Multi-Protocol Over ATM allows ATM edge devices such as routers,
69 bool "Per-VC IP filter kludge"
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
|
| D | phy-cadence-sierra.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
[all …]
|
| D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp-pcie-msm8996.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp.h"
47 * for cases when second lane needs different values
66 /* set of registers with offsets different per-PHY */
169 /* struct qmp_phy_cfg - per-PHY initialization config */
174 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
199 * struct qmp_phy - per-lane phy descriptor
204 * @tx: iomapped memory space for lane's tx
205 * @rx: iomapped memory space for lane's rx
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | video-interfaces.txt | 4 ---------------
21 #address-cells = <1>;
22 #size-cells = <0>;
37 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
41 specify #address-cells, #size-cells properties independently for the 'port'
44 Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
53 a device is partitioned into multiple data busses, e.g. 16-bit input port
54 divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
55 and data-shift properties can be used to assign physical data lines to each
59 --------------------------------
[all …]
|
| /kernel/linux/linux-5.10/Documentation/driver-api/media/ |
| D | csi2.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 MIPI CSI-2
8 CSI-2 is a data bus intended for transferring images from cameras to
14 -----------------
16 See :ref:`v4l2-mbus-pixelcode` for details on which media bus formats should
17 be used for CSI-2 interfaces.
20 -------------------
22 CSI-2 transmitter, such as a sensor or a TV tuner, drivers need to
23 provide the CSI-2 receiver with information on the CSI-2 bus
26 (:c:type:`v4l2_subdev_video_ops`->s_stream() callback). These
[all …]
|