| /arkcompiler/runtime_core/static_core/compiler/optimizer/optimizations/regalloc/ |
| D | working_ranges.h | 26 …explicit WorkingRanges(ArenaAllocator *allocator) : regular(allocator->Adapter()), physical(alloca… in WorkingRanges()
29 InstructionsRanges physical; // NOLINT(misc-non-private-member-variables-in-classes) member
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| D | reg_alloc_graph_coloring.cpp | 35 for (auto physicalInterval : ranges->physical) { in FillPhysicalNodes()
45 ig->Reserve(ranges->regular.size() + ranges->physical.size()); in BuildIG()
449 // skip physical intervals for unavailable registers, they do not affect allocation in InitWorkingRanges()
452 AddRange(interval, &ranges->physical); in InitWorkingRanges()
495 for (auto physical : ranges->physical) { in Presplit() local
496 …if (interval->GetLocation() == physical->GetLocation() && interval->IntersectsWith<true>(physical)… in Presplit()
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| /arkcompiler/runtime_core/compiler/optimizer/optimizations/regalloc/ |
| D | reg_alloc_graph_coloring.cpp | 25 ig->Reserve(ranges->regular.size() + ranges->physical.size()); in BuildIG()
29 for (auto physical_interval : ranges->physical) { in BuildIG()
57 // Current interval can intersect the physical one at the beginning of its live range in BuildIG()
58 // only if it's a call and physical interval's range was created for it. in BuildIG()
359 // skip physical intervals for unavailable registers, they do not affect allocation in InitWorkingRanges()
362 AddRange(interval, &ranges->physical); in InitWorkingRanges()
405 for (auto physical : ranges->physical) { in Presplit() local
406 … if (interval->GetLocation() == physical->GetLocation() && interval->IntersectsWith(physical)) { in Presplit()
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| D | reg_alloc_graph_coloring.h | 33 : regular(allocator->Adapter()), physical(allocator->Adapter()) in WorkingRanges()
38 InstructionsRanges physical; // NOLINT(misc-non-private-member-variables-in-classes) member
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/ |
| D | reg_alloc_basic.h | 73 MapleMap<uint32, regno_t> regMap; /* virtual-register-to-physical-register map */
74 MapleSet<uint8> liveReg; /* a set of currently live physical registers */
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| D | reg_info.h | 24 constexpr uint32 kBaseVirtualRegNO = 200; /* avoid conflicts between virtual and physical */
53 regno_t regNO = kInvalidRegNO; /* physical register assigned by register allocation */
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| D | reg_alloc_lsra.h | 551 /* physical register, using cg defined reg based on R0/V0. */
828 uint32 intParamMask = 0; /* (physical-register) parameter */
837 uint32 fpParamMask = 0; /* (physical-register) parameter */
838 uint64 blockForbiddenMask = 0; /* bit mask for forbidden physical reg */
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| D | pressure.h | 208 /* if define physical register, set hasPreg as true */
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| D | cg_irbuilder.h | 76 constexpr uint32 baseVirtualRegNO = 200; /* avoid conflicts between virtual and physical */
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| D | stackmap.h | 34 int64 value; // physical registerNO, stack frame offset, or immediate value
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| /arkcompiler/runtime_core/static_core/docs/bc_verification/ |
| D | absint_checks.md | 3 ### Physical compatibility of arguments to instructions and actual parameters to methods
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| /arkcompiler/runtime_core/docs/bc_verification/ |
| D | absint_checks.md | 3 ### Physical compatibility of arguments to instructions and actual parameters to methods
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| /arkcompiler/runtime_core/static_core/runtime/scheduler/ |
| D | worker_thread.h | 25 // Worker thread is a physical OS thread.
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| /arkcompiler/runtime_core/static_core/compiler/tests/ |
| D | liveness_analyzer_test.cpp | 765 // physical: [10-11] in TEST_F()
766 …// no intersection: physical's [10-11] range was created for the interval's instruction to block d… in TEST_F()
770 LifeIntervals physical(GetAllocator()); in TEST_F() local
771 physical.SetPhysicalReg(0U, DataType::INT64); // Make interval physical in TEST_F()
772 physical.AppendRange({10U, 11U}); in TEST_F()
773 EXPECT_FALSE(interval.IntersectsWith<true>(&physical)); in TEST_F()
776 // physical: [10-11] [20-21] in TEST_F()
781 physical.Clear(); in TEST_F()
782 physical.AppendRange({20U, 21U}); in TEST_F()
783 physical.AppendRange({10U, 11U}); in TEST_F()
[all …]
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/analysis/ |
| D | liveness_analyzer.h | 387 ss << " {physical}"; in ToString()
425 …// Interval can intersect the physical one at the beginning of its live range only if that physical in IntersectsWith()
429 // physical [-] [-] [-] in IntersectsWith()
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| /arkcompiler/runtime_core/static_core/verification/ |
| D | messages.yaml | 343 …${register} physical type is '${actual_type}'. But the expected physical type is '${expected_type}…
377 …Cannot make a call to '${name}'. Actual lambda type ${reg}'${actual_type}' (physical type '${physi…
378 …is not compatible with formal lambda type '${formal_type}' (physical type '${physical_formal_type}…
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/ |
| D | reg_alloc_lsra.cpp | 37 * is in 'active', the vreg occupies a physical register allocation and no other vreg can
38 * be allocated the same physical register.
406 * Prepare the free physical register pool for allocation.
407 * When a physical register is allocated, it is removed from the pool.
408 * The physical register is re-inserted into the pool when the associated live
693 /* Do not consider physical regs. */ in UpdateLiveIntervalByLiveIn()
1130 * reclaim the physical register associated with it. in UpdateCallQueueAtRetirement()
1243 * release physical reg assigned to free reg pool in RetireActive()
1255 /* find the best physical reg by freeUntilPos */
1468 * will either get an allocated physical register or a slot number in SpillOperand()
[all …]
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| D | reg_alloc_basic.cpp | 38 DEBUG_ASSERT(regMapIt->second < regInfo->GetAllRegNum(), "must be a physical register"); in HandleRegOpnd()
180 /* trying to allocate a physical register to opnd. return true if success */
366 /* remember the physical machine register assigned */ in AllocHandleDest()
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| D | peep.cpp | 690 /* === Physical Pre Form === */ in MAPLE_TRANSFORM_PHASE_REGISTER_CANSKIP()
701 /* === Physical Post Form === */ in MAPLE_TRANSFORM_PHASE_REGISTER_CANSKIP()
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| D | insn.cpp | 24 /* phi is not physical insn */
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| /arkcompiler/runtime_core/compiler/docs/ |
| D | reg_alloc_graph_coloring_doc.md | 55 …at the moment are assigned by colors, these colors are remapped back to physical register numbers …
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| /arkcompiler/runtime_core/static_core/compiler/docs/ |
| D | reg_alloc_graph_coloring_doc.md | 55 …at the moment are assigned by colors, these colors are remapped back to physical register numbers …
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| /arkcompiler/runtime_core/static_core/runtime/mem/gc/g1/ |
| D | g1-gc.h | 515 /// Flag indicates if we need to interrupt release physical pages to OS
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| /arkcompiler/runtime_core/static_core/irtoc/scripts/ |
| D | common.irt | 71 # Remove even registers from regmask for ARM32, because compiler conservatively uses two physical r…
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| /arkcompiler/runtime_core/compiler/optimizer/analysis/ |
| D | liveness_analyzer.h | 360 ss << " {physical}"; in ToString()
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