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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dbrcm,brcmstb-memc-ddr.yaml16 - brcm,brcmstb-memc-ddr-rev-b.1.x
17 - brcm,brcmstb-memc-ddr-rev-b.2.0
18 - brcm,brcmstb-memc-ddr-rev-b.2.1
19 - brcm,brcmstb-memc-ddr-rev-b.2.2
20 - brcm,brcmstb-memc-ddr-rev-b.2.3
21 - brcm,brcmstb-memc-ddr-rev-b.2.5
22 - brcm,brcmstb-memc-ddr-rev-b.2.6
23 - brcm,brcmstb-memc-ddr-rev-b.2.7
24 - brcm,brcmstb-memc-ddr-rev-b.2.8
25 - brcm,brcmstb-memc-ddr-rev-b.3.0
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/include/
Ddal_asic_id.h46 #define ASIC_REV_IS_TAHITI_P(rev) \ argument
47 ((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
49 #define ASIC_REV_IS_PITCAIRN_PM(rev) \ argument
50 ((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
52 #define ASIC_REV_IS_CAPEVERDE_M(rev) \ argument
53 ((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
55 #define ASIC_REV_IS_OLAND_M(rev) \ argument
56 ((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
58 #define ASIC_REV_IS_HAINAN_V(rev) \ argument
59 ((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
[all …]
/kernel/linux/linux-6.6/arch/mips/ath79/
Dsetup.c49 u32 rev = 0; in ath79_detect_sys_type() local
58 rev = id >> AR71XX_REV_ID_REVISION_SHIFT; in ath79_detect_sys_type()
59 rev &= AR71XX_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
81 rev = id & AR724X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
87 rev = id & AR724X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
93 rev = id & AR724X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
98 rev = id >> AR913X_REV_ID_REVISION_SHIFT; in ath79_detect_sys_type()
99 rev &= AR913X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
116 rev = id & AR933X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
122 rev = id & AR933X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/
Dadreno_device.c23 .rev = ADRENO_REV(2, 0, 0, 0),
34 .rev = ADRENO_REV(2, 0, 0, 1),
45 .rev = ADRENO_REV(2, 2, 0, ANY_ID),
56 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
67 .rev = ADRENO_REV(3, 0, 6, 0),
78 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
89 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
100 .rev = ADRENO_REV(4, 0, 5, ANY_ID),
111 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
122 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
[all …]
/kernel/linux/linux-5.10/arch/mips/ath79/
Dsetup.c58 u32 rev = 0; in ath79_detect_sys_type() local
67 rev = id >> AR71XX_REV_ID_REVISION_SHIFT; in ath79_detect_sys_type()
68 rev &= AR71XX_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
90 rev = id & AR724X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
96 rev = id & AR724X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
102 rev = id & AR724X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
107 rev = id >> AR913X_REV_ID_REVISION_SHIFT; in ath79_detect_sys_type()
108 rev &= AR913X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
125 rev = id & AR933X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
131 rev = id & AR933X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/include/
Ddal_asic_id.h46 #define ASIC_REV_IS_TAHITI_P(rev) \ argument
47 ((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
49 #define ASIC_REV_IS_PITCAIRN_PM(rev) \ argument
50 ((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
52 #define ASIC_REV_IS_CAPEVERDE_M(rev) \ argument
53 ((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
55 #define ASIC_REV_IS_OLAND_M(rev) \ argument
56 ((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
58 #define ASIC_REV_IS_HAINAN_V(rev) \ argument
59 ((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
[all …]
/kernel/linux/linux-6.6/arch/powerpc/kernel/
Dcpu_specs_44x.h13 .cpu_name = "440GR Rev. A",
25 .cpu_name = "440EP Rev. A",
38 .cpu_name = "440GR Rev. B",
50 .cpu_name = "440EP Rev. C",
63 .cpu_name = "440EP Rev. B",
99 { /* 440GP Rev. B */
102 .cpu_name = "440GP Rev. B",
111 { /* 440GP Rev. C */
114 .cpu_name = "440GP Rev. C",
123 { /* 440GX Rev. A */
[all …]
Dcpu_specs_40x.h110 { /* 405EX Rev. A/B with Security */
113 .cpu_name = "405EX Rev. A/B",
123 { /* 405EX Rev. C without Security */
126 .cpu_name = "405EX Rev. C",
136 { /* 405EX Rev. C with Security */
139 .cpu_name = "405EX Rev. C",
149 { /* 405EX Rev. D without Security */
152 .cpu_name = "405EX Rev. D",
162 { /* 405EX Rev. D with Security */
165 .cpu_name = "405EX Rev. D",
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Dmach-crag6410-module.c41 .reset_active_high = 1, /* Active high for Glenfarclas Rev 2 */
325 u8 rev; member
334 { .id = 0x01, .rev = 0xff, .name = "1250-EV1 Springbank" },
335 { .id = 0x02, .rev = 0xff, .name = "1251-EV1 Jura" },
336 { .id = 0x03, .rev = 0xff, .name = "1252-EV1 Glenlivet" },
337 { .id = 0x06, .rev = 0xff, .name = "WM8997-6721-CS96-EV1 Lapraoig" },
338 { .id = 0x07, .rev = 0xff, .name = "WM5110-6271 Deanston",
341 { .id = 0x08, .rev = 0xff, .name = "WM8903-6102 Tamdhu" },
342 { .id = 0x09, .rev = 0xff, .name = "WM1811A-6305 Adelphi" },
343 { .id = 0x0a, .rev = 0xff, .name = "WM8996-6272 Blackadder" },
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-s3c/
Dmach-crag6410-module.c37 .reset_active_high = 1, /* Active high for Glenfarclas Rev 2 */
312 u8 rev; member
321 { .id = 0x01, .rev = 0xff, .name = "1250-EV1 Springbank" },
322 { .id = 0x02, .rev = 0xff, .name = "1251-EV1 Jura" },
323 { .id = 0x03, .rev = 0xff, .name = "1252-EV1 Glenlivet" },
324 { .id = 0x06, .rev = 0xff, .name = "WM8997-6721-CS96-EV1 Lapraoig" },
325 { .id = 0x07, .rev = 0xff, .name = "WM5110-6271 Deanston",
328 { .id = 0x08, .rev = 0xff, .name = "WM8903-6102 Tamdhu" },
329 { .id = 0x09, .rev = 0xff, .name = "WM1811A-6305 Adelphi" },
330 { .id = 0x0a, .rev = 0xff, .name = "WM8996-6272 Blackadder" },
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dcpu-imx31.c21 unsigned int rev; member
23 { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
24 { .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
25 { .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
26 { .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
27 { .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
28 { .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 },
29 { .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 },
30 { .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 },
31 { .srev = 0x29, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_2_0 },
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-imx/
Dcpu-imx31.c21 unsigned int rev; member
23 { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
24 { .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
25 { .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
26 { .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
27 { .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
28 { .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 },
29 { .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 },
30 { .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 },
31 { .srev = 0x29, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_2_0 },
[all …]
/kernel/linux/linux-5.10/arch/x86/kernel/cpu/microcode/
Dintel.c97 if (mc_hdr->rev <= new_rev) in has_newer_microcode()
137 if (mc_hdr->rev <= mc_saved_hdr->rev) in save_microcode_patch()
319 uci->cpu_sig.rev)) in scan_microcode()
328 phdr->rev)) in scan_microcode()
368 csig.rev = intel_get_microcode_revision(); in collect_cpu_info_early()
380 unsigned int sig, pf, rev, total_size, data_size, date; in show_saved_mc() local
393 rev = uci.cpu_sig.rev; in show_saved_mc()
394 pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev); in show_saved_mc()
406 rev = mc_saved_header->rev; in show_saved_mc()
412 pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", in show_saved_mc()
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Did.c152 u8 dev_type, rev; in omap2xxx_check_revision() local
158 rev = (idcode >> 28) & 0x0f; in omap2xxx_check_revision()
162 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", in omap2xxx_check_revision()
163 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); in omap2xxx_check_revision()
353 u8 rev; in omap3xxx_check_revision() local
369 * hawkeye and rev. See TRM 1.5.2 Device Identification. in omap3xxx_check_revision()
370 * Note that rev does not map directly to our defined processor in omap3xxx_check_revision()
375 rev = (idcode >> 28) & 0xff; in omap3xxx_check_revision()
380 switch (rev) { in omap3xxx_check_revision()
412 switch (rev) { in omap3xxx_check_revision()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Did.c152 u8 dev_type, rev; in omap2xxx_check_revision() local
158 rev = (idcode >> 28) & 0x0f; in omap2xxx_check_revision()
162 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", in omap2xxx_check_revision()
163 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); in omap2xxx_check_revision()
353 u8 rev; in omap3xxx_check_revision() local
369 * hawkeye and rev. See TRM 1.5.2 Device Identification. in omap3xxx_check_revision()
370 * Note that rev does not map directly to our defined processor in omap3xxx_check_revision()
375 rev = (idcode >> 28) & 0xff; in omap3xxx_check_revision()
380 switch (rev) { in omap3xxx_check_revision()
412 switch (rev) { in omap3xxx_check_revision()
[all …]
/kernel/linux/linux-6.6/drivers/firmware/arm_scmi/
Dbase.c69 struct scmi_revision_info *rev = ph->get_priv(ph); in scmi_base_attributes_get() local
79 rev->num_protocols = attr_info->num_protocols; in scmi_base_attributes_get()
80 rev->num_agents = attr_info->num_agents; in scmi_base_attributes_get()
103 struct scmi_revision_info *rev = ph->get_priv(ph); in scmi_base_vendor_id_get() local
108 vendor_id = rev->sub_vendor_id; in scmi_base_vendor_id_get()
109 size = ARRAY_SIZE(rev->sub_vendor_id); in scmi_base_vendor_id_get()
112 vendor_id = rev->vendor_id; in scmi_base_vendor_id_get()
113 size = ARRAY_SIZE(rev->vendor_id); in scmi_base_vendor_id_get()
144 struct scmi_revision_info *rev = ph->get_priv(ph); in scmi_base_implementation_version_get() local
154 rev->impl_ver = le32_to_cpu(*impl_ver); in scmi_base_implementation_version_get()
[all …]
/kernel/linux/linux-6.6/arch/x86/kernel/cpu/microcode/
Dintel.c92 csig.rev = intel_get_microcode_revision(); in intel_cpu_collect_info()
250 if (mc_hdr->rev <= new_rev) in has_newer_microcode()
290 if (mc_hdr->rev <= mc_saved_hdr->rev) in save_microcode_patch()
374 uci->cpu_sig.rev)) in scan_microcode()
383 phdr->rev)) in scan_microcode()
448 print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); in show_ucode_info_early()
482 u32 rev, old_rev; in apply_microcode_early() local
493 rev = intel_get_microcode_revision(); in apply_microcode_early()
494 if (rev >= mc->hdr.rev) { in apply_microcode_early()
495 uci->cpu_sig.rev = rev; in apply_microcode_early()
[all …]
/kernel/linux/linux-5.10/drivers/firmware/arm_scmi/
Dbase.c62 struct scmi_revision_info *rev = handle->version; in scmi_base_attributes_get() local
72 rev->num_protocols = attr_info->num_protocols; in scmi_base_attributes_get()
73 rev->num_agents = attr_info->num_agents; in scmi_base_attributes_get()
96 struct scmi_revision_info *rev = handle->version; in scmi_base_vendor_id_get() local
100 vendor_id = rev->sub_vendor_id; in scmi_base_vendor_id_get()
101 size = ARRAY_SIZE(rev->sub_vendor_id); in scmi_base_vendor_id_get()
104 vendor_id = rev->vendor_id; in scmi_base_vendor_id_get()
105 size = ARRAY_SIZE(rev->vendor_id); in scmi_base_vendor_id_get()
136 struct scmi_revision_info *rev = handle->version; in scmi_base_implementation_version_get() local
146 rev->impl_ver = le32_to_cpu(*impl_ver); in scmi_base_implementation_version_get()
[all …]
/kernel/linux/linux-6.6/tools/testing/selftests/drivers/net/mlxsw/
Dmlxsw_lib.sh27 local rev=$1; shift
29 local rev2=${rev%+}
31 if [[ $rev2 != $rev ]]; then
40 local rev=$1; shift
44 if ! mlxsw_on_spectrum "$rev"; then
45 log_test_skip $src:$caller "(Spectrum-$rev only)"
54 local rev
56 for rev in "$@"; do
57 if __mlxsw_only_on_spectrum "$rev" "$caller" "$src"; then
/kernel/linux/linux-5.10/arch/arm64/lib/
Dcrc32.S27 CPU_BE( rev x3, x3 )
28 CPU_BE( rev x4, x4 )
29 CPU_BE( rev x5, x5 )
30 CPU_BE( rev x6, x6 )
58 CPU_BE( rev x3, x3 )
59 CPU_BE( rev x4, x4 )
60 CPU_BE( rev x5, x5 )
61 CPU_BE( rev x6, x6 )
71 CPU_BE( rev x3, x3 )
75 CPU_BE( rev w3, w3 )
/kernel/linux/linux-6.6/arch/powerpc/kvm/
Dbook3s_hv_rm_mmu.c68 void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev, in kvmppc_add_revmap_chain() argument
76 head = &kvm->arch.hpt.rev[i]; in kvmppc_add_revmap_chain()
79 tail = &kvm->arch.hpt.rev[head->back]; in kvmppc_add_revmap_chain()
82 rev->forw = i; in kvmppc_add_revmap_chain()
83 rev->back = head->back; in kvmppc_add_revmap_chain()
87 rev->forw = rev->back = pte_index; in kvmppc_add_revmap_chain()
148 struct revmap_entry *rev, in remove_revmap_chain() argument
159 ptel = rev->guest_rpte |= rcbits; in remove_revmap_chain()
166 next = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->forw]); in remove_revmap_chain()
167 prev = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->back]); in remove_revmap_chain()
[all …]
/kernel/linux/linux-5.10/arch/powerpc/kvm/
Dbook3s_hv_rm_mmu.c81 void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev, in kvmppc_add_revmap_chain() argument
89 head = &kvm->arch.hpt.rev[i]; in kvmppc_add_revmap_chain()
92 tail = &kvm->arch.hpt.rev[head->back]; in kvmppc_add_revmap_chain()
95 rev->forw = i; in kvmppc_add_revmap_chain()
96 rev->back = head->back; in kvmppc_add_revmap_chain()
100 rev->forw = rev->back = pte_index; in kvmppc_add_revmap_chain()
161 struct revmap_entry *rev, in remove_revmap_chain() argument
172 ptel = rev->guest_rpte |= rcbits; in remove_revmap_chain()
179 next = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->forw]); in remove_revmap_chain()
180 prev = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->back]); in remove_revmap_chain()
[all …]
/kernel/linux/linux-6.6/drivers/memory/
Dbrcmstb_memc.c181 .compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
185 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.0",
189 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
193 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2",
197 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3",
201 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.5",
205 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.6",
209 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.7",
213 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.8",
217 .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0",
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Dqcom.yaml419 - description: HP Chromebook x2 11c (newest rev)
430 - description: HP Chromebook x2 11c with LTE (newest rev)
446 - description: Lenovo Chromebook Duet 5 13 (newest rev)
456 - description: Google Kingoftown (newest rev)
482 - description: Acer Chromebook Spin 513 (newest rev)
503 - description: Acer Chromebook Spin 513 with KB Backlight (newest rev)
524 - description: Acer Chromebook Spin 513 with LTE (newest rev)
538 - description: Acer Chromebook 511 (newest rev)
557 - description: Acer Chromebook 511 without Touchscreen (newest rev)
567 - description: Google Mrbland with AUO panel (newest rev)
[all …]
/kernel/linux/linux-5.10/drivers/acpi/
Dpci_mcfg.c42 /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
46 #define AL_ECAM(table_id, rev, seg, ops) \ argument
47 { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
86 #define THUNDER_PEM_QUIRK(rev, node) \ argument
87 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
89 { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
91 { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
93 { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
95 { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
97 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
[all …]

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