| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | phy-rockchip-naneng-combphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
[all …]
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| D | rockchip-pcie-phy.txt | 1 Rockchip PCIE PHY
2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
13 Required properties for legacy PHY mode (deprecated):
14 - #phy-cells: must be 0
[all …]
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| D | rockchip,pcie3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PCIe v3 phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-pcie3-phy
16 - rockchip,rk3588-pcie3-phy
25 clock-names:
29 data-lanes:
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| /kernel/linux/linux-6.6/drivers/phy/rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
19 associated to the Rockchip ISP module present in RK3399 SoCs.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
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| D | phy-rockchip-snps-pcie3.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
56 struct phy *phy; member
67 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument
69 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_set_mode()
74 priv->mode = PHY_MODE_PCIE_RC; in rockchip_p3phy_set_mode()
77 priv->mode = PHY_MODE_PCIE_EP; in rockchip_p3phy_set_mode()
[all …]
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
3 obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o
4 obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
5 obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o
6 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
7 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
8 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
9 obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
10 obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | rockchip-pcie-ep.txt | 1 * Rockchip AXI PCIe Endpoint Controller DT description
4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
[all …]
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| D | rockchip-pcie-host.txt | 1 * Rockchip AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | rockchip,rk3399-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Endpoint
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
[all …]
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| D | rockchip-dw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16 PCIe IP and thus inherits all the common properties defined in
[all …]
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| D | rockchip,rk3399-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Root Port Bridge Host
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
[all …]
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| D | rockchip,rk3399-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Bridge Common Properties
10 - Shawn Lin <shawn.lin@rock-chips.com>
19 clock-names:
21 - const: aclk
22 - const: aclk-perf
23 - const: hclk
[all …]
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| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pcie-dw-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Rockchip SoCs.
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
19 #include <linux/phy/phy.h>
24 #include "pcie-designware.h"
34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
54 struct phy *phy; member
63 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, in rockchip_pcie_readl_apb() argument
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | rk3588.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
7 #include "rk3588-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
16 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
21 compatible = "rockchip,rk3588-i2s-tdm";
25 clock-names = "mclk_tx", "mclk_rx", "hclk";
26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
27 assigned-clock-parents = <&cru PLL_AUPLL>;
29 dma-names = "tx";
[all …]
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| D | rk3568.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
9 compatible = "rockchip,rk3568";
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
[all …]
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| D | rk3568-lubancat-2.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
17 compatible = "embedfire,lubancat-2", "rockchip,rk3568";
27 stdout-path = "serial2:1500000n8";
31 compatible = "gpio-leds";
[all …]
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| D | rk3399.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
19 associated to the Rockchip ISP module present in RK3399 SoCs.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
[all …]
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
3 obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o
4 obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
5 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
6 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
7 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
8 obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
9 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
10 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | rockchip-pcie-phy.txt | 1 Rockchip PCIE PHY
2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
13 Required properties for legacy PHY mode (deprecated):
14 - #phy-cells: must be 0
[all …]
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| /kernel/linux/linux-6.6/drivers/pci/controller/ |
| D | pcie-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
5 * Copyright (c) 2016 Rockchip, Inc.
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
20 #include <linux/phy/phy.h>
25 #include "pcie-rockchip.h"
27 int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) in rockchip_pcie_parse_dt() argument
29 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
31 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
[all …]
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| D | pcie-rockchip-host.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
5 * Copyright (c) 2016 Rockchip, Inc.
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
31 #include <linux/phy/phy.h>
37 #include "pcie-rockchip.h"
39 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip) in rockchip_pcie_enable_bw_int() argument
43 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); in rockchip_pcie_enable_bw_int()
45 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); in rockchip_pcie_enable_bw_int()
[all …]
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
5 * Copyright (c) 2016 Rockchip, Inc.
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
19 #include <linux/phy/phy.h>
24 #include "pcie-rockchip.h"
26 int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) in rockchip_pcie_parse_dt() argument
28 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
30 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
[all …]
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| D | pcie-rockchip-host.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
5 * Copyright (c) 2016 Rockchip, Inc.
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
34 #include <linux/phy/phy.h>
40 #include "pcie-rockchip.h"
42 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip) in rockchip_pcie_enable_bw_int() argument
46 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); in rockchip_pcie_enable_bw_int()
48 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); in rockchip_pcie_enable_bw_int()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/rockchip/ |
| D | grf.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip General Register Files (GRF)
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
[all …]
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