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/kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/
Djh7100.dtsi169 rstgen: reset-controller@11840000 { label
181 resets = <&rstgen JH7100_RSTN_I2C0_APB>;
194 resets = <&rstgen JH7100_RSTN_I2C1_APB>;
207 resets = <&rstgen JH7100_RSTN_GPIO_APB>;
221 resets = <&rstgen JH7100_RSTN_UART2_APB>;
234 resets = <&rstgen JH7100_RSTN_UART3_APB>;
247 resets = <&rstgen JH7100_RSTN_I2C2_APB>;
260 resets = <&rstgen JH7100_RSTN_I2C3_APB>;
273 resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
274 <&rstgen JH7100_RSTN_WDT>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/hwmon/
Dstarfive,jh71x0-temp.yaml67 resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
68 <&rstgen JH7100_RSTN_TEMP_APB>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dnvidia,tegra20-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
25 RSTGEN provides the registers needed to control resetting of each block in
Dnvidia,tegra124-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
25 RSTGEN provides the registers needed to control resetting of each block in