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Searched +full:sc8280xp +full:- +full:mdss (Results 1 – 7 of 7) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/msm/
Dqcom,sc8280xp-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC8280XP Mobile Display Subsystem
10 - Bjorn Andersson <andersson@kernel.org>
13 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sc8280xp-mdss
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Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
19 - enum:
20 - qcom,sc7180-dp
21 - qcom,sc7280-dp
22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dqcom,dispcc-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SC8280XP
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 power domains for the two MDSS instances on SC8280XP.
17 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
22 - qcom,sc8280xp-dispcc0
23 - qcom,sc8280xp-dispcc1
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/kernel/linux/linux-6.6/drivers/iommu/arm/arm-smmu/
Darm-smmu-qcom.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
12 #include "arm-smmu.h"
13 #include "arm-smmu-qcom.h"
15 #define QCOM_DUMMY_VAL -1
30 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in qcom_smmu_tlb_sync()
53 if (qsmmu->stall_enabled & BIT(idx)) in qcom_adreno_smmu_write_sctlr()
63 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_get_fault_info()
64 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_get_fault_info()
66 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); in qcom_adreno_smmu_get_fault_info()
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/
Dmsm_mdss.c2 * SPDX-License-Identifier: GPL-2.0
53 path0 = of_icc_get(dev, "mdp0-mem"); in msm_mdss_parse_data_bus_icc_path()
57 msm_mdss->path[0] = path0; in msm_mdss_parse_data_bus_icc_path()
58 msm_mdss->num_paths = 1; in msm_mdss_parse_data_bus_icc_path()
60 path1 = of_icc_get(dev, "mdp1-mem"); in msm_mdss_parse_data_bus_icc_path()
62 msm_mdss->path[1] = path1; in msm_mdss_parse_data_bus_icc_path()
63 msm_mdss->num_paths++; in msm_mdss_parse_data_bus_icc_path()
74 for (i = 0; i < msm_mdss->num_paths; i++) in msm_mdss_put_icc_path()
75 icc_put(msm_mdss->path[i]); in msm_mdss_put_icc_path()
82 for (i = 0; i < msm_mdss->num_paths; i++) in msm_mdss_icc_request_bw()
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dsc8280xp.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
13 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_kms.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
13 #include <linux/dma-buf.h>
62 struct dpu_kms *kms = s->private; in _dpu_danger_signal_status()
65 if (!kms->hw_mdp) { in _dpu_danger_signal_status()
72 pm_runtime_get_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
75 if (kms->hw_mdp->ops.get_danger_status) in _dpu_danger_signal_status()
76 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, in _dpu_danger_signal_status()
80 if (kms->hw_mdp->ops.get_safe_status) in _dpu_danger_signal_status()
81 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp, in _dpu_danger_signal_status()
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