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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Sierra PHY
10 This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
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Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-cadence-sierra.txt1 Cadence Sierra PHY
2 -----------------------
5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
7 - resets: Must contain an entry for each in reset-names.
9 - reset-names: Must include "sierra_reset" and "sierra_apb".
10 "sierra_reset" must control the reset line to the PHY.
11 "sierra_apb" must control the reset line to the APB PHY
13 - reg: register range for the PHY.
14 - #address-cells: Must be 1
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Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
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/kernel/linux/linux-5.10/drivers/phy/cadence/
Dphy-cadence-sierra.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence Sierra PHY Driver
14 #include <linux/phy/phy.h>
22 #include <dt-bindings/phy/phy.h>
24 /* PHY register offsets */
155 struct phy *phy; member
211 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()
213 writew(val, ctx->base + offset); in cdns_regmap_write()
221 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()
223 *val = readw(ctx->base + offset); in cdns_regmap_read()
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/kernel/linux/linux-6.6/drivers/phy/cadence/
Dphy-cadence-sierra.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence Sierra PHY Driver
10 #include <linux/clk-provider.h>
15 #include <linux/phy/phy.h>
23 #include <dt-bindings/phy/phy.h>
24 #include <dt-bindings/phy/phy-cadence.h>
29 /* PHY register offsets */
203 /* PHY PCS common registers */
209 /* PHY PCS lane registers */
216 /* PHY PMA common registers */
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
12 cmn_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
18 cmn_refclk1: clock-cmnrefclk1 {
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/
Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
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