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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dnvidia,tegra-audio-wm8903.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm8903.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra audio complex with WM8903 CODEC
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - items:
20 - pattern: '^[a-z0-9]+,tegra-audio-wm8903(-[a-z0-9]+)+$'
[all …]
/kernel/linux/linux-6.6/sound/soc/tegra/
Dtegra_wm8903.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra_wm8903.c - Tegra machine ASoC driver for boards using WM8903 codec.
6 * Copyright (C) 2010-2012 - NVIDIA, Inc.
26 #include "../codecs/wm8903.h"
57 struct tegra_machine *machine = snd_soc_card_get_drvdata(rtd->card); in tegra_wm8903_init()
58 struct snd_soc_card *card = rtd->card; in tegra_wm8903_init()
63 * forcing it to active-low. This means that all older device-trees in tegra_wm8903_init()
64 * which set the polarity to active-high are wrong and we need to fix in tegra_wm8903_init()
67 if (machine->asoc->hp_jack_gpio_active_low) { in tegra_wm8903_init()
68 bool active_low = gpiod_is_active_low(machine->gpiod_hp_det); in tegra_wm8903_init()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 # Tegra platform Support
3 snd-soc-tegra-pcm-objs := tegra_pcm.o
4 snd-soc-tegra-utils-objs += tegra_asoc_utils.o
5 snd-soc-tegra20-ac97-objs := tegra20_ac97.o
6 snd-soc-tegra20-das-objs := tegra20_das.o
7 snd-soc-tegra20-i2s-objs := tegra20_i2s.o
8 snd-soc-tegra20-spdif-objs := tegra20_spdif.o
9 snd-soc-tegra30-ahub-objs := tegra30_ahub.o
10 snd-soc-tegra30-i2s-objs := tegra30_i2s.o
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SoC Audio for the Tegra System-on-Chip"
10 Say Y or M here if you want support for SoC audio on Tegra.
63 Config to enable Audio Hub (AHUB) module, which comprises of a
64 switch called Audio Crossbar (AXBAR) used to configure or modify
65 the audio routing path between various HW accelerators present in
82 Config to enable the Inter-IC Sound (I2S) Controller which
83 implements full-duplex and bidirectional and single direction
84 point-to-point serial interfaces. It can interface with I2S
113 converts the multi-bit Pulse Code Modulation (PCM) audio input to
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dnvidia,tegra-audio-wm8903.txt1 NVIDIA Tegra audio complex
4 - compatible : "nvidia,tegra-audio-wm8903"
5 - clocks : Must contain an entry for each entry in clock-names.
6 See ../clocks/clock-bindings.txt for details.
7 - clock-names : Must include the following entries:
8 - pll_a
9 - pll_a_out0
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
11 - nvidia,model : The user-visible name of this sound complex.
12 - nvidia,audio-routing : A list of the connections between audio components.
[all …]
Dnvidia,tegra-audio-trimslice.txt1 NVIDIA Tegra audio complex for TrimSlice
4 - compatible : "nvidia,tegra-audio-trimslice"
5 - clocks : Must contain an entry for each entry in clock-names.
6 - clock-names : Must include the following entries:
7 "pll_a" (The Tegra clock of that name),
8 "pll_a_out0" (The Tegra clock of that name),
9 "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
10 - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
11 - nvidia,audio-codec : The phandle of the WM8903 audio codec
16 compatible = "nvidia,tegra-audio-trimslice";
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra20-tec.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
17 wm8903: wm8903@1a { label
18 compatible = "wlf,wm8903";
20 interrupt-parent = <&gpio>;
23 gpio-controller;
24 #gpio-cells = <2>;
26 micdet-cfg = <0>;
27 micdet-delay = <100>;
[all …]
Dtegra20-plutux.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
17 wm8903: wm8903@1a { label
18 compatible = "wlf,wm8903";
20 interrupt-parent = <&gpio>;
23 gpio-controller;
24 #gpio-cells = <2>;
26 micdet-cfg = <0>;
27 micdet-delay = <100>;
[all …]
Dtegra20-medcom-wide.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
7 model = "Avionic Design Medcom-Wide board";
8 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
15 stdout-path = "serial0:115200n8";
32 wm8903: wm8903@1a { label
33 compatible = "wlf,wm8903";
35 interrupt-parent = <&gpio>;
38 gpio-controller;
[all …]
Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
[all …]
Dtegra30-cardhu.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
16 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
17 * tegra30-cardhu-a04.dts.
20 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
22 * The (downstream internal) U-Boot of Cardhu display the board-id as
43 stdout-path = "serial0:115200n8";
[all …]
Dtegra20-harmony.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 hdmi-supply = <&vdd_5v0_hdmi>;
38 vdd-supply = <&hdmi_vdd_reg>;
39 pll-supply = <&hdmi_pll_reg>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
Dtegra20-seaboard.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39 hdmi-supply = <&vdd_hdmi>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
16 chassis-type = "convertible";
33 * pre-existing /chosen node to be available to insert the
[all …]
Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
32 * pre-existing /chosen node to be available to insert the
41 reserved-memory {
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra20-tec.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
17 wm8903: wm8903@1a { label
18 compatible = "wlf,wm8903";
20 interrupt-parent = <&gpio>;
23 gpio-controller;
24 #gpio-cells = <2>;
26 micdet-cfg = <0>;
27 micdet-delay = <100>;
[all …]
Dtegra20-plutux.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
17 wm8903: wm8903@1a { label
18 compatible = "wlf,wm8903";
20 interrupt-parent = <&gpio>;
23 gpio-controller;
24 #gpio-cells = <2>;
26 micdet-cfg = <0>;
27 micdet-delay = <100>;
[all …]
Dtegra20-medcom-wide.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
7 model = "Avionic Design Medcom-Wide board";
8 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
15 stdout-path = "serial0:115200n8";
32 wm8903: wm8903@1a { label
33 compatible = "wlf,wm8903";
35 interrupt-parent = <&gpio>;
38 gpio-controller;
[all …]
Dtegra30-cardhu.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
13 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
14 * tegra30-cardhu-a04.dts.
17 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
19 * The (downstream internal) U-Boot of Cardhu display the board-id as
40 stdout-path = "serial0:115200n8";
51 avdd-pexb-supply = <&ldo1_reg>;
52 vdd-pexb-supply = <&ldo1_reg>;
53 avdd-pex-pll-supply = <&ldo1_reg>;
[all …]
Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "tegra20-cpu-opp.dtsi"
19 stdout-path = "serial0:115200n8";
38 vdd-supply = <&hdmi_vdd_reg>;
39 pll-supply = <&hdmi_pll_reg>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
Dtegra20-harmony.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 hdmi-supply = <&vdd_5v0_hdmi>;
38 vdd-supply = <&hdmi_vdd_reg>;
39 pll-supply = <&hdmi_pll_reg>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
Dtegra20-seaboard.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39 hdmi-supply = <&vdd_hdmi>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20-cpu-opp.dtsi"
10 #include "tegra20-cpu-opp-microvolt.dtsi"
31 * pre-existing /chosen node to be available to insert the
40 reserved-memory {
41 #address-cells = <1>;
[all …]
/kernel/linux/linux-5.10/sound/soc/tegra/
Dtegra_wm8903.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra_wm8903.c - Tegra machine ASoC driver for boards using WM8903 codec.
6 * Copyright (C) 2010-2012 - NVIDIA, Inc.
29 #include "../codecs/wm8903.h"
33 #define DRV_NAME "tegra-snd-wm8903"
49 struct snd_soc_card *card = rtd->card; in tegra_wm8903_hw_params()
69 err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk); in tegra_wm8903_hw_params()
71 dev_err(card->dev, "Can't configure clocks\n"); in tegra_wm8903_hw_params()
78 dev_err(card->dev, "codec_dai clock not set\n"); in tegra_wm8903_hw_params()
117 struct snd_soc_dapm_context *dapm = w->dapm; in tegra_wm8903_event_int_spk()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SoC Audio for the Tegra System-on-Chip"
10 Say Y or M here if you want support for SoC audio on Tegra.
69 Config to enable Audio Hub (AHUB) module, which comprises of a
70 switch called Audio Crossbar (AXBAR) used to configure or modify
71 the audio routing path between various HW accelerators present in
90 Config to enable the Inter-IC Sound (I2S) Controller which
91 implements full-duplex and bidirectional and single direction
92 point-to-point serial interfaces. It can interface with I2S
101 converts the multi-bit Pulse Code Modulation (PCM) audio input to
[all …]

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