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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dsocionext,uniphier-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe PHY
11 PCIe controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
21 - socionext,uniphier-pxs3-pcie-phy
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
[all …]
Dsocionext,uniphier-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe host controller
10 UniPhier PCIe host controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dsocionext,uniphier-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe PHY
11 PCIe controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
21 - socionext,uniphier-pxs3-pcie-phy
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/designware-pcie.txt.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: "pci-ep.yaml#"
[all …]
Duniphier-pcie.txt1 Socionext UniPhier PCIe host controller bindings
3 This describes the devicetree bindings for PCIe host controller implemented
4 on Socionext UniPhier SoCs.
6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
7 It shares common functions with the PCIe DesignWare core driver and inherits
9 Documentation/devicetree/bindings/pci/designware-pcie.txt.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
[all …]
/kernel/linux/linux-6.6/drivers/phy/socionext/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 tristate "UniPhier USB2 PHY driver"
14 on UniPhier SoCs. This driver provides interface to interact
15 with USB 2.0 PHY that is part of the UniPhier SoC.
17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
26 on UniPhier SoCs. This controller supports USB3.0 and lower speed.
29 tristate "Uniphier PHY driver for PCIe controller"
35 Enable this to support PHY implemented in PCIe controller
36 on UniPhier SoCs. This driver supports LD20 and PXs3 SoCs.
[all …]
Dphy-uniphier-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller
80 writel(data, priv->base + PCL_PHY_TEST_I); in uniphier_pciephy_testio_write()
81 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
82 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
87 u32 val = readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_read()
126 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
129 writel(val, priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
136 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_deassert()
138 writel(val, priv->base + PCL_PHY_RESET); in uniphier_pciephy_deassert()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_PHY_UNIPHIER_USB2) += phy-uniphier-usb2.o
7 obj-$(CONFIG_PHY_UNIPHIER_USB3) += phy-uniphier-usb3hs.o phy-uniphier-usb3ss.o
8 obj-$(CONFIG_PHY_UNIPHIER_PCIE) += phy-uniphier-pcie.o
9 obj-$(CONFIG_PHY_UNIPHIER_AHCI) += phy-uniphier-ahci.o
/kernel/linux/linux-5.10/drivers/phy/socionext/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 tristate "UniPhier USB2 PHY driver"
14 on UniPhier SoCs. This driver provides interface to interact
15 with USB 2.0 PHY that is part of the UniPhier SoC.
17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
26 on UniPhier SoCs. This controller supports USB3.0 and lower speed.
29 tristate "Uniphier PHY driver for PCIe controller"
35 Enable this to support PHY implemented in PCIe controller
36 on UniPhier SoCs. This driver supports LD20 and PXs3 SoCs.
[all …]
Dphy-uniphier-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller
68 writel(data, priv->base + PCL_PHY_TEST_I); in uniphier_pciephy_testio_write()
69 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
70 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
82 val = readl(priv->base + PCL_PHY_TEST_O) & TESTO_DAT_MASK; in uniphier_pciephy_set_param()
97 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_set_param()
104 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
107 writel(val, priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
114 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_deassert()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_PHY_UNIPHIER_USB2) += phy-uniphier-usb2.o
7 obj-$(CONFIG_PHY_UNIPHIER_USB3) += phy-uniphier-usb3hs.o phy-uniphier-usb3ss.o
8 obj-$(CONFIG_PHY_UNIPHIER_PCIE) += phy-uniphier-pcie.o
9 obj-$(CONFIG_PHY_UNIPHIER_AHCI) += phy-uniphier-ahci.o
/kernel/linux/linux-5.10/drivers/pci/controller/dwc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
23 bool "TI DRA7xx PCIe controller Host Mode"
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
47 endpoint mode. There are two instances of PCIe controller in DRA7xx.
49 host-specific features PCI_DRA7XX_HOST must be selected and in order
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
6 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
7 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
8 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
9 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
10 obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
[all …]
/kernel/linux/linux-6.6/drivers/reset/
Dreset-uniphier.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/reset-controller.h>
22 #define UNIPHIER_RESET_ID_END ((unsigned int)(-1))
58 UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */
66 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */
69 UNIPHIER_RESETX(24, 0x2008, 2), /* PCIe */
80 UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
81 UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
82 UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
83 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro5 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
9 compatible = "socionext,uniphier-pro5";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 enable-method = "psci";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs3";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
[all …]
Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-ld20";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
[all …]
/kernel/linux/linux-6.6/drivers/pci/controller/dwc/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
6 obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
7 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
8 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
9 obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
10 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
18 bool "Amazon Annapurna Labs PCIe controller"
24 Say Y here to enable support of the Amazon's Annapurna Labs PCIe
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
27 required only for DT-based platforms. ACPI platforms with the
28 Annapurna Labs PCIe controller don't need to enable this.
31 tristate "Amlogic Meson PCIe controller"
38 and therefore the driver re-uses the DesignWare core functions to
45 bool "Axis ARTPEC-6 PCIe controller (host mode)"
[all …]
Dpcie-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for UniPhier SoCs
23 #include "pcie-designware.h"
73 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
[all …]
/kernel/linux/linux-5.10/drivers/reset/
Dreset-uniphier.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/reset-controller.h>
23 #define UNIPHIER_RESET_ID_END (unsigned int)(-1)
59 UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */
67 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */
70 UNIPHIER_RESETX(24, 0x2008, 2), /* PCIe */
81 UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
82 UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
83 UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
84 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/socionext/
Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro5 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
[all …]
Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-ld20";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]

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