Lines Matching +full:0 +full:xff0f0000
32 mcr p14, 0, \ch, c0, c5, 0
38 mcr p14, 0, \ch, c8, c0, 0
44 mcr p14, 0, \ch, c1, c0, 0
63 mov \rb, #0x80000000 @ physical base address
65 add \rb, \rb, #0x00050000 @ Ser3
67 add \rb, \rb, #0x00010000 @ Ser1
96 kputc #'0'
100 kputc #'0'
105 kputc #'0'
109 kputc #'0'
125 kputc #'0'
130 kputc #'0'
139 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
143 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
144 ARM( .inst 0xf57ff06f @ v7+ isb )
228 .word 0x04030201 @ endianness flag
229 .word 0x45454545 @ another magic number to indicate
252 mov r0, #0x17 @ angel_SWIreason_EnterSVC
253 ARM( swi 0x123456 ) @ angel_SWI_ARM
254 THUMB( svc 0xab ) @ angel_SWI_THUMB
291 and r4, r4, #0xf8000000
332 mov r5, #0 @ init dtb size to 0
348 ldr lr, [r6, #0]
350 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
352 ldr r1, =0xd00dfeed
372 bic r1, r1, #0x00ff0000
397 * pointed by r8. Try the typical 0x100 offset from start
403 add r0, r0, #0x100
430 bic r1, r1, #0x00ff0000
448 cmp r1, #0 @ already set
463 add r0, r0, #0x1000
466 ldr r2, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
468 ldr r2, =0xd00dfeed
484 mrc p15, 0, r1, c0, c1, 1 @ read ID_PFR1 register
485 tst r1, #0x10000 @ have generic timer?
494 cmp r0, #0
612 * r5 = appended dtb size (0 if not present)
638 1: ldr r1, [r11, #0] @ relocate entries in the GOT
657 1: ldr r1, [r11, #0] @ relocate entries in the GOT
666 not_relocated: mov r0, #0
711 __HVC(0) @ otherwise bounce to hyp mode
740 params: ldr r0, =0x10000100 @ params_phys for RPC
756 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
759 and \tmp, \tmp, #0xf @ cache line size encoding
790 mov r0, #0x3f @ 4G, the whole
791 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
792 mcr p15, 0, r0, c6, c7, 1
794 mov r0, #0x80 @ PR7
795 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
796 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
797 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
799 mov r0, #0xc000
800 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
801 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
803 mov r0, #0
804 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
805 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
806 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
807 mrc p15, 0, r0, c1, c0, 0 @ read control reg
809 orr r0, r0, #0x002d @ .... .... ..1. 11.1
810 orr r0, r0, #0x1000 @ ...1 .... .... ....
812 mcr p15, 0, r0, c1, c0, 0 @ write control reg
814 mov r0, #0
815 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
816 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
820 mov r0, #0x3f @ 4G, the whole
821 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
823 mov r0, #0x80 @ PR7
824 mcr p15, 0, r0, c2, c0, 0 @ cache on
825 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
827 mov r0, #0xc000
828 mcr p15, 0, r0, c5, c0, 0 @ access permission
830 mov r0, #0
831 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
836 mrc p15, 0, r0, c1, c0, 0 @ read control reg
838 orr r0, r0, #0x000d @ .... .... .... 11.1
840 mov r0, #0
841 mcr p15, 0, r0, c1, c0, 0 @ write control reg
844 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
848 #define CB_BITS 0x08
850 #define CB_BITS 0x0c
854 bic r3, r3, #0xff @ Align the pointer
855 bic r3, r3, #0x3f00
863 add r10, r9, #0x10000000 @ a reasonable RAM size
864 mov r1, #0x12 @ XN|U + section mapping
869 bic r1, r1, #0x1c @ clear XN|U + C + B
870 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
882 orr r1, r6, #0x04 @ ensure B is set for this
891 0: str r1, [r0], #4
894 bls 0b
901 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
904 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
910 mcr p15, 7, r0, c15, c0, 0
916 mov r6, #CB_BITS | 0x12 @ U
918 mov r0, #0
919 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
920 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
921 mrc p15, 0, r0, c1, c0, 0 @ read control reg
922 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
923 orr r0, r0, #0x0030
926 mov r0, #0
927 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
935 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
936 tst r11, #0xf @ VMSA
937 movne r6, #CB_BITS | 0x02 @ !XN
939 mov r0, #0
940 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
941 tst r11, #0xf @ VMSA
942 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
944 mrc p15, 0, r0, c1, c0, 0 @ read control reg
946 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
947 orr r0, r0, #0x003c @ write buffer
953 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
955 movne r1, #0xfffffffd @ domain 0 = client
957 bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
958 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
959 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
960 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
962 mcr p15, 0, r0, c7, c5, 4 @ ISB
963 mcr p15, 0, r0, c1, c0, 0 @ load control register
964 mrc p15, 0, r0, c1, c0, 0 @ and read it back
965 mov r0, #0
966 mcr p15, 0, r0, c7, c5, 4 @ ISB
971 mov r6, #CB_BITS | 0x12 @ U
973 mov r0, #0
974 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
975 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
976 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
977 mrc p15, 0, r0, c1, c0, 0 @ read control reg
978 orr r0, r0, #0x1000 @ I-cache enable
980 mov r0, #0
981 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
987 orr r0, r0, #0x000d @ Write buffer, mmu
990 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
991 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
994 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
995 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
1017 mrc p15, 0, r9, c0, c0 @ get processor ID
1031 1: ldr r1, [r12, #0] @ get value
1049 * We match an entry using: ((real_id ^ match) & mask) == 0
1058 .word 0x41000000 @ old ARM ID
1059 .word 0xff00f000
1067 .word 0x41007000 @ ARM7/710
1068 .word 0xfff8fe00
1076 .word 0x41807200 @ ARM720T (writethrough)
1077 .word 0xffffff00
1083 .word 0x41007400 @ ARM74x
1084 .word 0xff00ff00
1089 .word 0x41009400 @ ARM94x
1090 .word 0xff00ff00
1095 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
1096 .word 0xff0ffff0
1101 .word 0x00007000 @ ARM7 IDs
1102 .word 0x0000f000
1112 .word 0x4401a100 @ sa110 / sa1100
1113 .word 0xffffffe0
1118 .word 0x6901b110 @ sa1110
1119 .word 0xfffffff0
1124 .word 0x56056900
1125 .word 0xffffff00 @ PXA9xx
1130 .word 0x56158000 @ PXA168
1131 .word 0xfffff000
1136 .word 0x56050000 @ Feroceon
1137 .word 0xff0f0000
1144 .long 0x41009260 @ Old Feroceon
1145 .long 0xff00fff0
1151 .word 0x66015261 @ FA526
1152 .word 0xff01fff1
1159 .word 0x00020000 @ ARMv4T
1160 .word 0x000f0000
1165 .word 0x00050000 @ ARMv5TE
1166 .word 0x000f0000
1171 .word 0x00060000 @ ARMv5TEJ
1172 .word 0x000f0000
1177 .word 0x0007b000 @ ARMv6
1178 .word 0x000ff000
1183 .word 0x000f0000 @ new CPU Id
1184 .word 0x000f0000
1189 .word 0 @ unrecognised type
1190 .word 0
1206 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1224 mrc p15, 0, r0, c1, c0
1225 bic r0, r0, #0x000d
1226 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1227 mov r0, #0
1228 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1229 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1230 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1234 mrc p15, 0, r0, c1, c0
1235 bic r0, r0, #0x000d
1236 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1237 mov r0, #0
1238 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1243 mrc p15, 0, r0, c1, c0
1244 bic r0, r0, #0x000d
1245 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1246 mov r0, #0
1247 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1248 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1253 mrc p15, 0, r0, c1, c0
1255 bic r0, r0, #0x0005
1257 bic r0, r0, #0x0004
1259 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1260 mov r0, #0
1262 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1264 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1265 mcr p15, 0, r0, c7, c10, 4 @ DSB
1266 mcr p15, 0, r0, c7, c5, 4 @ ISB
1290 mov r3, #0
1291 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1294 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1296 bcs 2b @ entries 63 to 0
1298 bcs 1b @ segments 7 to 0
1300 teq r2, #0
1301 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1302 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1308 mov r1, #0
1309 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1310 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1311 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1315 mov r1, #0
1317 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1318 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1319 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1320 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1327 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1328 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1329 mov r10, #0
1331 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1339 0: cmp r0, r11 @ finished?
1341 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1343 b 0b
1345 mcr p15, 0, r10, c7, c10, 4 @ DSB
1346 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1347 mcr p15, 0, r10, c7, c10, 4 @ DSB
1348 mcr p15, 0, r10, c7, c5, 4 @ ISB
1354 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
1356 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1357 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1365 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1389 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1390 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1391 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1398 mov r1, #0
1399 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1414 mov r2, #0
1423 add r2, r2, #'0'
1430 teq r2, #0
1433 mov r1, #0x00020000
1439 teq r0, #0
1446 mov r0, #0
1452 mov r11, #0
1499 mov r0, #0 @ must be 0
1519 ldr r3, =0xa001 @ CRC-16 polynomial
1520 0: subs r2, r2, #4
1525 bic ip, ip, #0x00ff0000
1534 b 0b
1538 __kaslr_seed: .long 0
1539 __kaslr_offset: .long 0
1546 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1547 bic r0, r0, #0x5 @ disable MMU and caches
1548 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1557 adr r1, 0f @ clean the region of code we
1576 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
1577 tst r1, #0x1 @ MMU enabled at HYP?
1589 mcr p15, 4, r1, c1, c0, 0
1591 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1608 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
1609 tst r0, #0x1 @ MMU enabled?
1617 adr r0, 0f @ switch to our stack
1621 mov r5, #0 @ appended DTB size
1622 mov r7, #0xFFFFFFFF @ machine ID
1625 0: .long .L_user_stack_end - .