Lines Matching +full:1 +full:a01000
12 #address-cells = <1>;
13 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <1>;
35 #address-cells = <1>;
49 CPU1: cpu@1 {
53 reg = <1>;
191 interrupts = <1 10 0x304>;
217 #hwlock-cells = <1>;
239 q6@1 {
243 qcom,smd-edge = <1>;
270 #address-cells = <1>;
273 qcom,ipc-1 = <&l2cc 8 4>;
280 #qcom,smem-state-cells = <1>;
283 modem_smsm: modem@1 {
284 reg = <1>;
343 #address-cells = <1>;
344 #size-cells = <1>;
379 interrupts = <1 1 0x301>,
380 <1 2 0x301>,
381 <1 3 0x301>;
409 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
415 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
421 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
427 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
440 cell-index = <1>;
444 #address-cells = <1>;
445 #size-cells = <1>;
463 pinctrl-1 = <&i2c1_pins_sleep>;
469 #address-cells = <1>;
483 #address-cells = <1>;
484 #size-cells = <1>;
493 pinctrl-1 = <&i2c2_pins_sleep>;
498 #address-cells = <1>;
511 #address-cells = <1>;
512 #size-cells = <1>;
517 pinctrl-1 = <&i2c3_pins_sleep>;
524 #address-cells = <1>;
537 #address-cells = <1>;
538 #size-cells = <1>;
544 pinctrl-1 = <&i2c4_pins_sleep>;
555 gsbi5: gsbi@1a200000 {
562 #address-cells = <1>;
563 #size-cells = <1>;
566 gsbi5_serial: serial@1a240000 {
576 gsbi5_spi: spi@1a280000 {
581 pinctrl-1 = <&spi5_sleep>;
586 #address-cells = <1>;
598 #address-cells = <1>;
599 #size-cells = <1>;
615 pinctrl-1 = <&i2c6_pins_sleep>;
633 #address-cells = <1>;
634 #size-cells = <1>;
651 pinctrl-1 = <&i2c7_pins_sleep>;
662 rng@1a500000 {
674 pm8821: pmic@1 {
680 #address-cells = <1>;
707 #address-cells = <1>;
747 interrupts = <39 1>;
752 pwrkey@1c {
756 interrupts = <50 1>, <51 1>;
812 #address-cells = <1>;
813 #size-cells = <1>;
828 #clock-cells = <1>;
829 #reset-cells = <1>;
830 #thermal-sensor-cells = <1>;
836 #clock-cells = <1>;
837 #reset-cells = <1>;
843 #clock-cells = <1>;
844 #reset-cells = <1>;
864 #clock-cells = <1>;
938 #reset-cells = <1>;
969 #reset-cells = <1>;
1000 #reset-cells = <1>;
1015 sata_phy0: phy@1b400000 {
1058 #dma-cells = <1>;
1068 #dma-cells = <1>;
1078 #dma-cells = <1>;
1084 #address-cells = <1>;
1085 #size-cells = <1>;
1103 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1120 no-1-8-v;
1121 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1138 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1145 tcsr: syscon@1a400000 {
1168 &gfx3d 1
1200 &gfx3d1 1
1237 qcom,gpu-pwrlevel@1 {
1251 #address-cells = <1>;
1274 <&dsi0_phy 1>,
1275 <&dsi0_phy 1>;
1279 #address-cells = <1>;
1288 port@1 {
1289 reg = <1>;
1299 #clock-cells = <1>;
1314 #iommu-cells = <1>;
1330 #iommu-cells = <1>;
1346 #iommu-cells = <1>;
1362 #iommu-cells = <1>;
1376 pcie: pci@1b500000 {
1386 num-lanes = <1>;
1393 #interrupt-cells = <1>;
1395 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1430 #address-cells = <1>;
1439 port@1 {
1440 reg = <1>;
1482 #address-cells = <1>;
1491 port@1 {
1492 reg = <1>;
1573 etb@1a01000 {
1589 tpiu@1a03000 {
1612 #address-cells = <1>;
1621 port@1 {
1622 reg = <1>;
1638 funnel@1a04000 {
1646 #address-cells = <1>;
1662 port@1 {
1663 reg = <1>;
1691 etm@1a1c000 {
1709 etm@1a1d000 {
1727 etm@1a1e000 {
1745 etm@1a1f000 {