Lines Matching +full:write +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define U2DCR_SPEOREN (1 << 27) /* Short Packet EOR INTR generation Enable */
21 #define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */
28 #define U2DCR_UDE (1 << 0) /* U2D Enable */
32 #define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */
33 #define U2DINT_SOF (1 << 30) /* Interrupt - SOF */
34 #define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */
35 #define U2DINT_RU (1 << 28) /* Interrupt - Resume */
36 #define U2DINT_SU (1 << 27) /* Interrupt - Suspend */
37 #define U2DINT_RS (1 << 26) /* Interrupt - Reset */
38 #define U2DINT_DPE (1 << 25) /* Interrupt - Data Packet Error */
39 #define U2DINT_FIFOERR (0x4) /* Interrupt - endpoint FIFO error */
40 #define U2DINT_PACKETCMP (0x2) /* Interrupt - endpoint packet complete */
41 #define U2DINT_SPACKETCMP (0x1) /* Interrupt - endpoint short packet complete */
50 #define U2DOTGCR_OTGEN (1 << 31) /* On-The-Go Enable */
51 #define U2DOTGCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocal Port Support */
52 #define U2DOTGCR_AHNP (1 << 29) /* A-device Host Negotiation Protocal Support */
53 #define U2DOTGCR_BHNP (1 << 28) /* B-device Host Negotiation Protocal Enable */
57 #define U2DOTGCR_IESI (1 << 13) /* OTG interrupt Enable */
66 #define U2DOTGCR_ULE (1 << 0) /* ULPI Wrapper Enable */
90 #define U2DOTGUSR_S6A (1 << 30) /* ULPI Serial Mode (6-pin) Active */
91 #define U2DOTGUSR_S3A (1 << 29) /* ULPI Serial Mode (3-pin) Active */
103 #define U2DOTGUCR_RNW (1 << 24) /* Read or Write operation */
105 #define U2DOTGUCR_WDATA (0xff << 8) /* The data for a WRITE command */
111 #define U2DP3CR_VPVMBEN (0x1 << 2) /* Host Port 3 Vp/Vm Block Enable */
114 #define U2DCSR0 (0x0100) /* U2D Control/Status Register - Endpoint 0 */
120 #define U2DCSR0_DME (1 << 3) /* DMA Enable */
125 #define U2DCSR(x) (0x0100 + ((x) << 2)) /* U2D Control/Status Register - Endpoint x */
133 #define U2DCSR_FST (1 << 5) /* Force STALL, write 1 set */
134 #define U2DCSR_SST (1 << 4) /* Sent STALL, write 1 clear */
135 #define U2DCSR_DME (1 << 3) /* DMA Enable */
136 #define U2DCSR_TRN (1 << 2) /* Tx/Rx NAK, write 1 clear */
137 #define U2DCSR_PC (1 << 1) /* Packet Complete, write 1 clear */
140 #define U2DBCR0 (0x0200) /* U2D Byte Count Register - Endpoint 0 */
141 #define U2DBCR(x) (0x0200 + ((x) << 2)) /* U2D Byte Count Register - Endpoint x */
143 #define U2DDR0 (0x0300) /* U2D Data Register - Endpoint 0 */
145 #define U2DEPCR(x) (0x0400 + ((x) << 2)) /* U2D Configuration Register - Endpoint x */
146 #define U2DEPCR_EE (1 << 0) /* Endpoint Enable */
152 #define U2DEN0 (0x0504) /* U2D Endpoint Information Register - Endpoint 0 */
153 #define U2DEN(x) (0x0504 + ((x) << 2)) /* U2D Endpoint Information Register - Endpoint x */
156 #define U2DMACSR0 (0x1000) /* U2DMA Control/Status Register - Channel 0 */
157 #define U2DMACSR(x) (0x1000 + ((x) << 2)) /* U2DMA Control/Status Register - Channel x */
158 #define U2DMACSR_RUN (1 << 31) /* Run Bit (read / write) */
159 #define U2DMACSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
160 #define U2DMACSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
163 #define U2DMACSR_RASIRQEN (1 << 23) /* Request After Cnannel Stopped Interrupt Enable */
170 #define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */
172 #define U2DMACSR_ENDINTR (1 << 2) /* End Interrupt (read / write 1 clear) */
173 #define U2DMACSR_STARTINTR (1 << 1) /* Start Interrupt (read / write 1 clear) */
174 #define U2DMACSR_BUSERRINTR (1 << 0) /* Bus Error Interrupt (read / write 1 clear) */
179 #define U2DMABR0 (0x1100) /* U2DMA Branch Register - Channel 0 */
180 #define U2DMABR(x) (0x1100 + (x) << 2) /* U2DMA Branch Register - Channel x */
182 #define U2DMADADR0 (0x1200) /* U2DMA Descriptor Address Register - Channel 0 */
183 #define U2DMADADR(x) (0x1200 + (x) * 0x10) /* U2DMA Descriptor Address Register - Channel x */
187 #define U2DMASADR0 (0x1204) /* U2DMA Source Address Register - Channel 0 */
188 #define U2DMASADR(x) (0x1204 + (x) * 0x10) /* U2DMA Source Address Register - Channel x */
189 #define U2DMATADR0 (0x1208) /* U2DMA Target Address Register - Channel 0 */
190 #define U2DMATADR(x) (0x1208 + (x) * 0x10) /* U2DMA Target Address Register - Channel x */
192 #define U2DMACMDR0 (0x120C) /* U2DMA Command Address Register - Channel 0 */
193 #define U2DMACMDR(x) (0x120C + (x) * 0x10) /* U2DMA Command Address Register - Channel x */
196 #define U2DMACMDR_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
197 #define U2DMACMDR_ENDIRQEN (1 << 21) /* End Interrupt Enable */
199 #define U2DMACMDR_LEN (0x07ff) /* length mask (max = 2K - 1) */