Lines Matching +full:0 +full:xfee00000

21  * 0 special
39 #define IA64_SPURIOUS_INT_VECTOR	0x0f
42  * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
44 #define IA64_CPEP_VECTOR		0x1c	/* corrected platform error polling vector */
45 #define IA64_CMCP_VECTOR		0x1d	/* corrected machine-check polling vector */
46 #define IA64_CPE_VECTOR			0x1e	/* corrected platform error interrupt vector */
47 #define IA64_CMC_VECTOR			0x1f	/* corrected machine-check interrupt vector */
49  * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
50  * Use vectors 0x30-0xe7 as the default device vector range for ia64.
60 #define IA64_IRQ_MOVE_VECTOR		0x30	/* "move IRQ" IPI */
61 #define IA64_DEF_FIRST_DEVICE_VECTOR	0x31
63 #define IA64_DEF_FIRST_DEVICE_VECTOR	0x30
65 #define IA64_DEF_LAST_DEVICE_VECTOR	0xe7
71 #define IA64_MCA_RENDEZ_VECTOR		0xe8	/* MCA rendez interrupt */
72 #define IA64_PERFMON_VECTOR		0xee	/* performance monitor interrupt vector */
73 #define IA64_TIMER_VECTOR		0xef	/* use highest-prio group 15 interrupt for timer */
74 #define	IA64_MCA_WAKEUP_VECTOR		0xf0	/* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
75 #define IA64_IPI_LOCAL_TLB_FLUSH	0xfc	/* SMP flush local TLB */
76 #define IA64_IPI_RESCHEDULE		0xfd	/* SMP reschedule */
77 #define IA64_IPI_VECTOR			0xfe	/* inter-processor interrupt vector */
85 #define IA64_IPI_DEFAULT_BASE_ADDR	0xfee00000
89         IA64_IPI_DM_INT =       0x0,    /* pend an external interrupt */
90         IA64_IPI_DM_PMI =       0x2,    /* pend a PMI */
91         IA64_IPI_DM_NMI =       0x4,    /* pend an NMI (vector 2) */
92         IA64_IPI_DM_INIT =      0x5,    /* pend an INIT interrupt */
93         IA64_IPI_DM_EXTINT =    0x7,    /* pend an 8259-compatible interrupt. */
131 static inline int irq_prepare_move(int irq, int cpu) { return 0; }  in irq_prepare_move()
137 	ia64_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);  in ia64_native_resend_irq()