Lines Matching +full:ia32 +full:- +full:3 +full:a
1 /* SPDX-License-Identifier: GPL-2.0 */
8 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
9 * chapter 11 IA-64 Processor Abstraction Layer
11 * Copyright (C) 1998-2001 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
21 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
30 * Note that some of these calls use a static-register only calling
36 #define PAL_CACHE_INIT 3 /* initialize i/d cache */
66 #define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
83 #define PAL_TEST_PROC 258 /* perform late processor self-test */
87 #define PAL_GET_PSTATE 262 /* get the current P-state */
88 #define PAL_SET_PSTATE 263 /* set the P-state */
94 #define PAL_GET_PSTATE_TYPE_INSTANT 3
112 #define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
113 #define PAL_STATUS_EINVAL (-2) /* Invalid argument */
114 #define PAL_STATUS_ERROR (-3) /* Error */
115 #define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
120 #define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */
129 /* Processor cache type at a particular level in the hierarchy */
134 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
148 #define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
157 at : 2, /* 2-1 Cache mem attr*/
158 reserved : 5, /* 7-3 Reserved */
159 associativity : 8, /* 16-8 Associativity*/
160 line_size : 8, /* 23-17 Line size */
161 stride : 8, /* 31-24 Stride */
162 store_latency : 8, /*39-32 Store latency*/
163 load_latency : 8, /* 47-40 Load latency*/
164 store_hints : 8, /* 55-48 Store hints*/
165 load_hints : 8; /* 63-56 Load hints */
175 u32 alias_boundary : 8, /* 39-32 aliased addr
179 tag_ls_bit : 8, /* 47-40 LSb of addr*/
180 tag_ms_bit : 8, /* 55-48 MSb of addr*/
181 reserved : 8; /* 63-56 Reserved */
223 #define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
224 #define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
234 tagprot_lsb : 6, /* Least -do- */
262 #define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
278 #define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
285 u64 cache_type : 8, /* 7-0 cache type */
286 level : 8, /* 15-8 level of the
290 way : 8, /* 23-16 way in the set
292 part : 8, /* 31-24 part of the
295 reserved : 32; /* 63-32 is reserved*/
298 u64 cache_type : 8, /* 7-0 cache type */
299 level : 8, /* 15-8 level of the
303 way : 8, /* 23-16 way in the set
305 part : 8, /* 31-24 part of the
308 mesi : 8, /* 39-32 cache line
311 start : 8, /* 47-40 lsb of data to
314 length : 8, /* 55-48 #bits to
317 trigger : 8; /* 63-56 Trigger error
318 * by doing a load
343 #define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
351 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
372 #define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
390 * a rendezvous.
413 hd : 1, /* Non-essential hw
434 pm : 1, /* Precise min-state save area */
476 se : 1, /* Shared error. MCA in a
503 mesi : 3, /* Cache line state */
517 is : 1, /* instruction set (1 == ia32) */
554 is : 1, /* instruction set (1 == ia32) */
578 * during cache-cache
590 is : 1, /* instruction set (1 == ia32) */
620 is : 1, /* instruction set (1 == ia32) */
625 reserved3 : 3,
633 level : 3, /* Level of failure */
650 is : 1, /* instruction set (1 == ia32) */
749 * architectural state save area. The other 3 KB is scratch space
755 u64 pmsa_gr[15]; /* GR1 - GR15 */
756 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
757 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
774 * A zero status value indicates call completed without error.
775 * A negative status value indicates reason of call failure.
776 * A positive status value indicates success but an
889 features_avail->pal_bus_features_val = iprv.v0; in ia64_pal_bus_get_features()
891 features_status->pal_bus_features_val = iprv.v1; in ia64_pal_bus_get_features()
893 features_control->pal_bus_features_val = iprv.v2; in ia64_pal_bus_get_features()
915 conf->pcci_status = iprv.status; in ia64_pal_cache_config_info()
916 conf->pcci_info_1.pcci1_data = iprv.v0; in ia64_pal_cache_config_info()
917 conf->pcci_info_2.pcci2_data = iprv.v1; in ia64_pal_cache_config_info()
918 conf->pcci_reserved = iprv.v2; in ia64_pal_cache_config_info()
933 prot->pcpi_status = iprv.status; in ia64_pal_cache_prot_info()
934 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff; in ia64_pal_cache_prot_info()
935 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32; in ia64_pal_cache_prot_info()
936 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff; in ia64_pal_cache_prot_info()
937 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32; in ia64_pal_cache_prot_info()
938 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff; in ia64_pal_cache_prot_info()
939 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32; in ia64_pal_cache_prot_info()
969 /* Initialize the tags and data of a data or unified cache line of
982 /* Read the data and tag of a processor controlled cache line for diags */
1005 /* Write the data and tag of a processor-controlled cache line for diags */
1056 /* Switch from IA64-system environment to IA-32 system environment */
1157 /* Get the current P-state information */
1167 /* Set the P-state */
1210 /* Ensure that all outstanding transactions in a processor are completed or that any
1276 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1313 /* Register a platform dependent location with PAL to which it can save
1314 * minimal processor state in the event of a machine check or initialization
1350 * self-test and the required alignment of memory.
1384 pm_info->ppmi_data = iprv.v0; in ia64_pal_perf_mon_info()
1436 * Put everything in a struct so we avoid the global offset table whenever
1454 return -1; in ia64_get_ptce()
1458 ptce->base = iprv.v0; in ia64_get_ptce()
1459 ptce->count[0] = iprv.v1 >> 32; in ia64_get_ptce()
1460 ptce->count[1] = iprv.v1 & 0xffffffff; in ia64_get_ptce()
1461 ptce->stride[0] = iprv.v2 >> 32; in ia64_get_ptce()
1462 ptce->stride[1] = iprv.v2 & 0xffffffff; in ia64_get_ptce()
1500 hints->ph_data = iprv.v1; in ia64_pal_rse_info()
1517 * This is usually called in IA-32 mode.
1527 /* Perform the second phase of processor self-test. */
1564 pal_min_version->pal_version_val = iprv.v0; in ia64_pal_version()
1567 pal_cur_version->pal_version_val = iprv.v1; in ia64_pal_version()
1602 tc_info->pti_val = iprv.v0; in ia64_pal_vm_info()
1658 vm_info_1->pvi1_val = iprv.v0; in ia64_pal_vm_summary()
1660 vm_info_2->pvi2_val = iprv.v1; in ia64_pal_vm_summary()
1698 /* Read a translation register */
1705 tr_valid->piv_val = iprv.v0; in ia64_pal_tr_read()
1720 #define PAL_VISIBILITY_INVAL_ARG -2
1721 #define PAL_VISIBILITY_ERROR -3
1790 mapping->overview.overview_data = iprv.v0; in ia64_pal_logical_to_phys()
1791 mapping->ppli1.ppli1_data = iprv.v1; in ia64_pal_logical_to_phys()
1792 mapping->ppli2.ppli2_data = iprv.v2; in ia64_pal_logical_to_phys()
1817 info->num_shared = iprv.v0; in ia64_pal_cache_shared_info()
1818 info->ppli1.ppli1_data = iprv.v1; in ia64_pal_cache_shared_info()
1819 info->ppli2.ppli2_data = iprv.v2; in ia64_pal_cache_shared_info()