Lines Matching +full:non +full:- +full:cacheable
1 /* SPDX-License-Identifier: GPL-2.0 */
47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
51 #define ICACHE_SIZE 0x4000 /* instruction - 16k */
52 #define DCACHE_SIZE 0x2000 /* data - 8k */
56 #define ICACHE_SIZE 0x8000 /* instruction - 32k */
57 #define DCACHE_SIZE 0x8000 /* data - 32k */
61 #define ICACHE_SIZE 0x2000 /* instruction - 8k */
62 #define DCACHE_SIZE 0x2000 /* data - 8k */
68 #define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
69 #define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
95 * register region as non-cacheable. And then we map all our RAM as
96 * cacheable and supervisor access only.
114 * For the non-MMU enabled case we map all of RAM as cacheable.