Lines Matching +full:reg +full:- +full:addr
18 * only the performance is affected. Much worse is that such code is non-
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
92 #include <asm/unaligned-emul.h>
110 void __user *addr, unsigned int __user *pc) in emulate_load_store_insn() argument
119 orig31 = regs->regs[31]; in emulate_load_store_insn()
131 * can assume therefore that the code is MIPS-aware and in emulate_load_store_insn()
166 if (!access_ok(addr, 4)) in emulate_load_store_insn()
168 LoadW(addr, value, res); in emulate_load_store_insn()
172 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
175 if (!access_ok(addr, 2)) in emulate_load_store_insn()
177 LoadHW(addr, value, res); in emulate_load_store_insn()
181 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
197 if (!access_ok(addr, 2)) { in emulate_load_store_insn()
201 LoadHWE(addr, value, res); in emulate_load_store_insn()
207 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
210 if (!access_ok(addr, 4)) { in emulate_load_store_insn()
214 LoadWE(addr, value, res); in emulate_load_store_insn()
220 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
223 if (!access_ok(addr, 2)) { in emulate_load_store_insn()
227 LoadHWUE(addr, value, res); in emulate_load_store_insn()
233 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
236 if (!access_ok(addr, 2)) { in emulate_load_store_insn()
241 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
242 StoreHWE(addr, value, res); in emulate_load_store_insn()
249 if (!access_ok(addr, 4)) { in emulate_load_store_insn()
254 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
255 StoreWE(addr, value, res); in emulate_load_store_insn()
270 if (!access_ok(addr, 2)) in emulate_load_store_insn()
275 LoadHW(addr, value, res); in emulate_load_store_insn()
277 LoadHWE(addr, value, res); in emulate_load_store_insn()
279 LoadHW(addr, value, res); in emulate_load_store_insn()
285 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
289 if (!access_ok(addr, 4)) in emulate_load_store_insn()
294 LoadW(addr, value, res); in emulate_load_store_insn()
296 LoadWE(addr, value, res); in emulate_load_store_insn()
298 LoadW(addr, value, res); in emulate_load_store_insn()
304 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
308 if (!access_ok(addr, 2)) in emulate_load_store_insn()
313 LoadHWU(addr, value, res); in emulate_load_store_insn()
315 LoadHWUE(addr, value, res); in emulate_load_store_insn()
317 LoadHWU(addr, value, res); in emulate_load_store_insn()
323 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
329 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
330 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
331 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
332 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
333 * instructions on 32-bit kernels. in emulate_load_store_insn()
335 if (!access_ok(addr, 4)) in emulate_load_store_insn()
338 LoadWU(addr, value, res); in emulate_load_store_insn()
342 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
346 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
352 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
353 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
354 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
355 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
356 * instructions on 32-bit kernels. in emulate_load_store_insn()
358 if (!access_ok(addr, 8)) in emulate_load_store_insn()
361 LoadDW(addr, value, res); in emulate_load_store_insn()
365 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
369 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
373 if (!access_ok(addr, 2)) in emulate_load_store_insn()
377 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
381 StoreHW(addr, value, res); in emulate_load_store_insn()
383 StoreHWE(addr, value, res); in emulate_load_store_insn()
385 StoreHW(addr, value, res); in emulate_load_store_insn()
393 if (!access_ok(addr, 4)) in emulate_load_store_insn()
397 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
401 StoreW(addr, value, res); in emulate_load_store_insn()
403 StoreWE(addr, value, res); in emulate_load_store_insn()
405 StoreW(addr, value, res); in emulate_load_store_insn()
415 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
416 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
417 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
418 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
419 * instructions on 32-bit kernels. in emulate_load_store_insn()
421 if (!access_ok(addr, 8)) in emulate_load_store_insn()
425 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
426 StoreDW(addr, value, res); in emulate_load_store_insn()
432 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
447 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_insn()
479 fpr = ¤t->thread.fpu.fpr[wd]; in emulate_load_store_insn()
483 if (!access_ok(addr, sizeof(*fpr))) in emulate_load_store_insn()
498 res = __copy_from_user_inatomic(fpr, addr, in emulate_load_store_insn()
519 if (!access_ok(addr, sizeof(*fpr))) in emulate_load_store_insn()
532 res = __copy_to_user_inatomic(addr, fpr, sizeof(*fpr)); in emulate_load_store_insn()
586 regs->cp0_epc = origpc; in emulate_load_store_insn()
587 regs->regs[31] = orig31; in emulate_load_store_insn()
609 /* Recode table from 16-bit register notation to 32-bit GPR. */
612 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
616 void __user *addr) in emulate_load_store_microMIPS() argument
621 unsigned int reg = 0, rvar; in emulate_load_store_microMIPS() local
630 origpc = regs->cp0_epc; in emulate_load_store_microMIPS()
631 orig31 = regs->regs[31]; in emulate_load_store_microMIPS()
638 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc); in emulate_load_store_microMIPS()
641 contpc = regs->cp0_epc + 2; in emulate_load_store_microMIPS()
648 contpc = regs->cp0_epc + 4; in emulate_load_store_microMIPS()
679 reg = insn.mm_x_format.rd; in emulate_load_store_microMIPS()
688 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
689 if (reg == 31) in emulate_load_store_microMIPS()
692 if (!access_ok(addr, 8)) in emulate_load_store_microMIPS()
695 LoadW(addr, value, res); in emulate_load_store_microMIPS()
698 regs->regs[reg] = value; in emulate_load_store_microMIPS()
699 addr += 4; in emulate_load_store_microMIPS()
700 LoadW(addr, value, res); in emulate_load_store_microMIPS()
703 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
707 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
708 if (reg == 31) in emulate_load_store_microMIPS()
711 if (!access_ok(addr, 8)) in emulate_load_store_microMIPS()
714 value = regs->regs[reg]; in emulate_load_store_microMIPS()
715 StoreW(addr, value, res); in emulate_load_store_microMIPS()
718 addr += 4; in emulate_load_store_microMIPS()
719 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
720 StoreW(addr, value, res); in emulate_load_store_microMIPS()
727 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
728 if (reg == 31) in emulate_load_store_microMIPS()
731 if (!access_ok(addr, 16)) in emulate_load_store_microMIPS()
734 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
737 regs->regs[reg] = value; in emulate_load_store_microMIPS()
738 addr += 8; in emulate_load_store_microMIPS()
739 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
742 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
750 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
751 if (reg == 31) in emulate_load_store_microMIPS()
754 if (!access_ok(addr, 16)) in emulate_load_store_microMIPS()
757 value = regs->regs[reg]; in emulate_load_store_microMIPS()
758 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
761 addr += 8; in emulate_load_store_microMIPS()
762 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
763 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
772 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
773 rvar = reg & 0xf; in emulate_load_store_microMIPS()
774 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
776 if (reg & 0x10) { in emulate_load_store_microMIPS()
777 if (!access_ok(addr, 4 * (rvar + 1))) in emulate_load_store_microMIPS()
780 if (!access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
785 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
786 LoadW(addr, value, res); in emulate_load_store_microMIPS()
789 addr += 4; in emulate_load_store_microMIPS()
790 regs->regs[i] = value; in emulate_load_store_microMIPS()
792 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
793 LoadW(addr, value, res); in emulate_load_store_microMIPS()
796 addr += 4; in emulate_load_store_microMIPS()
797 regs->regs[30] = value; in emulate_load_store_microMIPS()
799 if (reg & 0x10) { in emulate_load_store_microMIPS()
800 LoadW(addr, value, res); in emulate_load_store_microMIPS()
803 regs->regs[31] = value; in emulate_load_store_microMIPS()
808 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
809 rvar = reg & 0xf; in emulate_load_store_microMIPS()
810 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
812 if (reg & 0x10) { in emulate_load_store_microMIPS()
813 if (!access_ok(addr, 4 * (rvar + 1))) in emulate_load_store_microMIPS()
816 if (!access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
821 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
822 value = regs->regs[i]; in emulate_load_store_microMIPS()
823 StoreW(addr, value, res); in emulate_load_store_microMIPS()
826 addr += 4; in emulate_load_store_microMIPS()
828 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
829 value = regs->regs[30]; in emulate_load_store_microMIPS()
830 StoreW(addr, value, res); in emulate_load_store_microMIPS()
833 addr += 4; in emulate_load_store_microMIPS()
835 if (reg & 0x10) { in emulate_load_store_microMIPS()
836 value = regs->regs[31]; in emulate_load_store_microMIPS()
837 StoreW(addr, value, res); in emulate_load_store_microMIPS()
845 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
846 rvar = reg & 0xf; in emulate_load_store_microMIPS()
847 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
849 if (reg & 0x10) { in emulate_load_store_microMIPS()
850 if (!access_ok(addr, 8 * (rvar + 1))) in emulate_load_store_microMIPS()
853 if (!access_ok(addr, 8 * rvar)) in emulate_load_store_microMIPS()
859 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
860 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
863 addr += 4; in emulate_load_store_microMIPS()
864 regs->regs[i] = value; in emulate_load_store_microMIPS()
866 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
867 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
870 addr += 8; in emulate_load_store_microMIPS()
871 regs->regs[30] = value; in emulate_load_store_microMIPS()
873 if (reg & 0x10) { in emulate_load_store_microMIPS()
874 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
877 regs->regs[31] = value; in emulate_load_store_microMIPS()
886 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
887 rvar = reg & 0xf; in emulate_load_store_microMIPS()
888 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
890 if (reg & 0x10) { in emulate_load_store_microMIPS()
891 if (!access_ok(addr, 8 * (rvar + 1))) in emulate_load_store_microMIPS()
894 if (!access_ok(addr, 8 * rvar)) in emulate_load_store_microMIPS()
900 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
901 value = regs->regs[i]; in emulate_load_store_microMIPS()
902 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
905 addr += 8; in emulate_load_store_microMIPS()
907 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
908 value = regs->regs[30]; in emulate_load_store_microMIPS()
909 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
912 addr += 8; in emulate_load_store_microMIPS()
914 if (reg & 0x10) { in emulate_load_store_microMIPS()
915 value = regs->regs[31]; in emulate_load_store_microMIPS()
916 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
933 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
960 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
961 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
967 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_microMIPS()
981 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
985 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
989 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
993 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
997 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
1001 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
1005 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
1011 reg = insn.mm16_m_format.rlist; in emulate_load_store_microMIPS()
1012 rvar = reg + 1; in emulate_load_store_microMIPS()
1013 if (!access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
1016 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
1017 LoadW(addr, value, res); in emulate_load_store_microMIPS()
1020 addr += 4; in emulate_load_store_microMIPS()
1021 regs->regs[i] = value; in emulate_load_store_microMIPS()
1023 LoadW(addr, value, res); in emulate_load_store_microMIPS()
1026 regs->regs[31] = value; in emulate_load_store_microMIPS()
1031 reg = insn.mm16_m_format.rlist; in emulate_load_store_microMIPS()
1032 rvar = reg + 1; in emulate_load_store_microMIPS()
1033 if (!access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
1036 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
1037 value = regs->regs[i]; in emulate_load_store_microMIPS()
1038 StoreW(addr, value, res); in emulate_load_store_microMIPS()
1041 addr += 4; in emulate_load_store_microMIPS()
1043 value = regs->regs[31]; in emulate_load_store_microMIPS()
1044 StoreW(addr, value, res); in emulate_load_store_microMIPS()
1055 reg = reg16to32[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1059 reg = reg16to32[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1063 reg = reg16to32st[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1067 reg = reg16to32st[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1071 reg = insn.mm16_r5_format.rt; in emulate_load_store_microMIPS()
1075 reg = insn.mm16_r5_format.rt; in emulate_load_store_microMIPS()
1079 reg = reg16to32[insn.mm16_r3_format.rt]; in emulate_load_store_microMIPS()
1087 if (!access_ok(addr, 2)) in emulate_load_store_microMIPS()
1090 LoadHW(addr, value, res); in emulate_load_store_microMIPS()
1093 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1097 if (!access_ok(addr, 2)) in emulate_load_store_microMIPS()
1100 LoadHWU(addr, value, res); in emulate_load_store_microMIPS()
1103 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1107 if (!access_ok(addr, 4)) in emulate_load_store_microMIPS()
1110 LoadW(addr, value, res); in emulate_load_store_microMIPS()
1113 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1119 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1120 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1121 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1122 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1123 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1125 if (!access_ok(addr, 4)) in emulate_load_store_microMIPS()
1128 LoadWU(addr, value, res); in emulate_load_store_microMIPS()
1131 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1135 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1141 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1142 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1143 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1144 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1145 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1147 if (!access_ok(addr, 8)) in emulate_load_store_microMIPS()
1150 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
1153 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1157 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1161 if (!access_ok(addr, 2)) in emulate_load_store_microMIPS()
1164 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1165 StoreHW(addr, value, res); in emulate_load_store_microMIPS()
1171 if (!access_ok(addr, 4)) in emulate_load_store_microMIPS()
1174 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1175 StoreW(addr, value, res); in emulate_load_store_microMIPS()
1183 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1184 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1185 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1186 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1187 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1189 if (!access_ok(addr, 8)) in emulate_load_store_microMIPS()
1192 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1193 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
1199 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1203 regs->cp0_epc = contpc; /* advance or branch */ in emulate_load_store_microMIPS()
1212 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
1213 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
1235 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr) in emulate_load_store_MIPS16e() argument
1239 int reg; in emulate_load_store_MIPS16e() local
1247 origpc = regs->cp0_epc; in emulate_load_store_MIPS16e()
1248 orig31 = regs->regs[31]; in emulate_load_store_MIPS16e()
1277 reg = reg16to32[mips16inst.ri64.ry]; in emulate_load_store_MIPS16e()
1281 reg = reg16to32[mips16inst.ri64.ry]; in emulate_load_store_MIPS16e()
1285 reg = 29; /* GPRSP */ in emulate_load_store_MIPS16e()
1292 reg = reg16to32[mips16inst.ri.rx]; in emulate_load_store_MIPS16e()
1307 reg = reg16to32[mips16inst.ri.rx]; in emulate_load_store_MIPS16e()
1311 reg = reg16to32[mips16inst.ri.rx]; in emulate_load_store_MIPS16e()
1331 reg = 29; /* GPRSP */ in emulate_load_store_MIPS16e()
1335 reg = reg16to32[mips16inst.rri.ry]; in emulate_load_store_MIPS16e()
1347 if (!access_ok(addr, 2)) in emulate_load_store_MIPS16e()
1350 LoadHW(addr, value, res); in emulate_load_store_MIPS16e()
1354 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1358 if (!access_ok(addr, 2)) in emulate_load_store_MIPS16e()
1361 LoadHWU(addr, value, res); in emulate_load_store_MIPS16e()
1365 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1371 if (!access_ok(addr, 4)) in emulate_load_store_MIPS16e()
1374 LoadW(addr, value, res); in emulate_load_store_MIPS16e()
1378 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1384 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1385 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1386 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1387 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1388 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1390 if (!access_ok(addr, 4)) in emulate_load_store_MIPS16e()
1393 LoadWU(addr, value, res); in emulate_load_store_MIPS16e()
1397 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1401 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1408 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1409 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1410 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1411 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1412 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1414 if (!access_ok(addr, 8)) in emulate_load_store_MIPS16e()
1417 LoadDW(addr, value, res); in emulate_load_store_MIPS16e()
1421 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1425 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1429 if (!access_ok(addr, 2)) in emulate_load_store_MIPS16e()
1433 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1434 StoreHW(addr, value, res); in emulate_load_store_MIPS16e()
1441 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */ in emulate_load_store_MIPS16e()
1442 if (!access_ok(addr, 4)) in emulate_load_store_MIPS16e()
1446 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1447 StoreW(addr, value, res); in emulate_load_store_MIPS16e()
1456 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1457 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1458 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1459 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1460 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1462 if (!access_ok(addr, 8)) in emulate_load_store_MIPS16e()
1466 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1467 StoreDW(addr, value, res); in emulate_load_store_MIPS16e()
1473 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1492 regs->cp0_epc = origpc; in emulate_load_store_MIPS16e()
1493 regs->regs[31] = orig31; in emulate_load_store_MIPS16e()
1523 1, regs, regs->cp0_badvaddr); in do_ade()
1527 if (regs->cp0_badvaddr == regs->cp0_epc) in do_ade()
1543 if (get_isa16_mode(regs->cp0_epc)) { in do_ade()
1546 * 16-bit mode? in do_ade()
1548 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc)) in do_ade()
1558 (void __user *)regs->cp0_badvaddr); in do_ade()
1569 (void __user *)regs->cp0_badvaddr); in do_ade()
1585 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc); in do_ade()