Lines Matching +full:1 +full:l
30 l.movhi rd,hi(-KERNELBASE) ;\
31 l.add rd,rd,rs
34 l.movhi gpr,0x0
37 l.movhi gpr,hi(symbol) ;\
38 l.ori gpr,gpr,lo(symbol)
54 #define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
55 #define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14)
57 #define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
58 #define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15)
60 #define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
61 #define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16)
63 #define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
64 #define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7)
66 #define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
67 #define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8)
69 #define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
70 #define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9)
73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
74 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
77 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
80 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
83 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
85 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
86 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
88 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
89 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
97 #define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2)
98 #define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2)
100 #define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3)
101 #define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3)
103 #define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4)
104 #define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4)
106 #define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5)
107 #define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5)
109 #define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6)
110 #define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6)
113 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
114 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
116 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
117 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
119 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
120 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
122 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
123 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
125 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
126 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
135 #define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30)
136 #define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30)
138 #define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10)
139 #define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10)
141 #define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1)
142 #define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1)
145 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
146 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
148 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
149 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
151 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
152 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
160 l.mfspr t1,r0,SPR_COREID ;\
161 l.slli t1,t1,2 ;\
162 l.add reg,reg,t1 ;\
164 l.lwz reg,0(t1)
169 l.lwz reg,0(t1)
177 l.mfspr r10,r0,SPR_COREID ;\
178 l.slli r10,r10,2 ;\
179 l.add r30,r30,r10 ;\
181 l.lwz r10,0(r30)
187 l.lwz r10,0(r30)
223 l.mfspr r30,r0,SPR_ESR_BASE ;\
224 l.andi r30,r30,SPR_SR_SM ;\
225 l.sfeqi r30,0 ;\
227 l.bnf 2f /* kernel_mode */ ;\
229 1: /* user_mode: */ ;\
232 l.lwz r1,(TI_KSP)(r30) ;\
238 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
241 l.sw PT_GPR12(r30),r12 ;\
243 l.mfspr r12,r0,SPR_EPCR_BASE ;\
244 l.sw PT_PC(r30),r12 ;\
245 l.mfspr r12,r0,SPR_ESR_BASE ;\
246 l.sw PT_SR(r30),r12 ;\
249 l.sw PT_GPR30(r30),r12 ;\
252 l.sw PT_GPR10(r30),r12 ;\
255 l.sw PT_SP(r30),r12 ;\
257 l.sw PT_GPR4(r30),r4 ;\
258 l.mfspr r4,r0,SPR_EEAR_BASE ;\
259 /* r12 == 1 if we come from syscall */ ;\
263 l.mfspr r30,r0,SPR_SR ;\
264 l.andi r30,r30,SPR_SR_DSX ;\
265 l.ori r30,r30,(EXCEPTION_SR) ;\
266 l.mtspr r0,r30,SPR_ESR_BASE ;\
269 l.mtspr r0,r30,SPR_EPCR_BASE ;\
270 l.rfe
278 * l.ori r3,r0,0x1 ;\
279 * l.mtspr r0,r3,SPR_SR ;\
280 * l.movhi r3,hi(0xf0000100) ;\
281 * l.ori r3,r3,lo(0xf0000100) ;\
282 * l.jr r3 ;\
283 * l.nop 1
298 l.addi r1,r3,0x0 ;\
299 l.addi r10,r9,0x0 ;\
301 l.jal _emergency_print ;\
302 l.ori r3,r0,lo(_string_unhandled_exception) ;\
303 l.mfspr r3,r0,SPR_NPC ;\
304 l.jal _emergency_print_nr ;\
305 l.andi r3,r3,0x1f00 ;\
307 l.jal _emergency_print ;\
308 l.ori r3,r0,lo(_string_epc_prefix) ;\
309 l.jal _emergency_print_nr ;\
310 l.mfspr r3,r0,SPR_EPCR_BASE ;\
311 l.jal _emergency_print ;\
312 l.ori r3,r0,lo(_string_nl) ;\
314 l.addi r3,r1,0x0 ;\
315 l.addi r9,r10,0x0 ;\
322 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
325 l.sw PT_GPR12(r30),r12 ;\
326 l.mfspr r12,r0,SPR_EPCR_BASE ;\
327 l.sw PT_PC(r30),r12 ;\
328 l.mfspr r12,r0,SPR_ESR_BASE ;\
329 l.sw PT_SR(r30),r12 ;\
332 l.sw PT_GPR30(r30),r12 ;\
335 l.sw PT_GPR10(r30),r12 ;\
338 l.sw PT_SP(r30),r12 ;\
339 l.sw PT_GPR13(r30),r13 ;\
342 l.sw PT_GPR4(r30),r4 ;\
343 l.mfspr r4,r0,SPR_EEAR_BASE ;\
344 /* r12 == 1 if we come from syscall */ ;\
347 l.ori r30,r0,(EXCEPTION_SR) ;\
348 l.mtspr r0,r30,SPR_ESR_BASE ;\
351 l.mtspr r0,r30,SPR_EPCR_BASE ;\
352 l.rfe
363 l.jr r13
364 l.nop
375 // l.mtspr r0,r0,SPR_TTMR
384 // l.mtspr r0,r0,SPR_TTMR
407 l.j boot_dtlb_miss_handler
408 l.nop
412 l.j boot_itlb_miss_handler
413 l.nop
515 l.or r25,r0,r3 /* pointer to fdt */
521 l.ori r3,r0,0x1
522 l.mtspr r0,r3,SPR_SR
530 l.movhi r3,hi(SPR_TTMR_CR)
531 l.mtspr r0,r3,SPR_TTMR
565 l.mfspr r26,r0,SPR_COREID
566 l.sfeq r26,r0
567 l.bnf secondary_wait
568 l.nop
577 l.sw TI_KSP(r31), r1
579 l.ori r4,r0,0x0
593 1:
594 l.sw (0)(r28),r0
595 l.sfltu r28,r30
596 l.bf 1b
597 l.addi r28,r28,4
600 l.jal _ic_enable
601 l.nop
604 l.jal _dc_enable
605 l.nop
608 l.jal _flush_tlb
609 l.nop
618 l.mfspr r30,r0,SPR_SR
619 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
620 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
621 l.or r30,r30,r28
622 l.mtspr r0,r30,SPR_SR
623 l.nop
624 l.nop
625 l.nop
626 l.nop
627 l.nop
628 l.nop
629 l.nop
630 l.nop
631 l.nop
632 l.nop
633 l.nop
634 l.nop
635 l.nop
636 l.nop
637 l.nop
638 l.nop
641 l.nop 5
644 l.lwz r3,0(r25) /* load magic from fdt into r3 */
645 l.movhi r4,hi(OF_DT_HEADER)
646 l.ori r4,r4,lo(OF_DT_HEADER)
647 l.sfeq r3,r4
648 l.bf _fdt_found
649 l.nop
651 l.or r25,r0,r0
654 l.or r3,r0,r25
656 l.jalr r24
657 l.nop
698 l.jr r30
699 l.nop
703 * I N V A L I D A T E T L B e n t r i e s
707 l.addi r7,r0,128 /* Maximum number of sets */
708 1:
709 l.mtspr r5,r0,0x0
710 l.mtspr r6,r0,0x0
712 l.addi r5,r5,1
713 l.addi r6,r6,1
714 l.sfeq r7,r0
715 l.bnf 1b
716 l.addi r7,r7,-1
718 l.jr r9
719 l.nop
725 l.mfspr r25,r0,SPR_UPR
726 l.andi r25,r25,SPR_UPR_PMP
727 l.sfeq r25,r0
728 l.bf secondary_check_release
729 l.nop
734 l.mtspr r0,r25,SPR_EVBAR
737 l.mfspr r25,r0,SPR_SR
738 l.ori r25,r25,SPR_SR_IEE
739 l.mtspr r0,r25,SPR_SR
742 l.mfspr r25,r0,SPR_PICMR
743 l.ori r25,r25,0xffff
744 l.mtspr r0,r25,SPR_PICMR
747 l.mfspr r25,r0,SPR_PMR
749 l.or r25,r25,r3
750 l.mtspr r0,r25,SPR_PMR
753 l.mtspr r0,r0,SPR_EVBAR
760 l.mfspr r25,r0,SPR_COREID
763 l.lwz r3,0(r4)
764 l.sfeq r25,r3
765 l.bnf secondary_wait
766 l.nop
775 l.lwz r10,0(r30)
776 l.addi r1,r10,THREAD_SIZE
778 l.sw TI_KSP(r30),r1
780 l.jal _ic_enable
781 l.nop
783 l.jal _dc_enable
784 l.nop
786 l.jal _flush_tlb
787 l.nop
792 l.mfspr r30,r0,SPR_SR
793 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
794 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
795 l.or r30,r30,r28
800 * Then EPCR is set to secondary_start and then a l.rfe is issued to
803 l.mtspr r0,r30,SPR_ESR_BASE
805 l.mtspr r0,r30,SPR_EPCR_BASE
806 l.rfe
810 l.jr r30
811 l.nop
824 l.mfspr r24,r0,SPR_UPR
825 l.andi r26,r24,SPR_UPR_ICP
826 l.sfeq r26,r0
827 l.bf 9f
828 l.nop
831 l.mfspr r6,r0,SPR_SR
832 l.addi r5,r0,-1
833 l.xori r5,r5,SPR_SR_ICE
834 l.and r5,r6,r5
835 l.mtspr r0,r5,SPR_SR
839 If BS=1, 32;
842 l.mfspr r24,r0,SPR_ICCFGR
843 l.andi r26,r24,SPR_ICCFGR_CBS
844 l.srli r28,r26,7
845 l.ori r30,r0,16
846 l.sll r14,r30,r28
852 l.andi r26,r24,SPR_ICCFGR_NCS
853 l.srli r28,r26,3
854 l.ori r30,r0,1
855 l.sll r16,r30,r28
858 l.addi r6,r0,0
859 l.sll r5,r14,r28
860 // l.mul r5,r14,r16
861 // l.trap 1
862 // l.addi r5,r0,IC_SIZE
863 1:
864 l.mtspr r0,r6,SPR_ICBIR
865 l.sfne r6,r5
866 l.bf 1b
867 l.add r6,r6,r14
868 // l.addi r6,r6,IC_LINE
871 l.mfspr r6,r0,SPR_SR
872 l.ori r6,r6,SPR_SR_ICE
873 l.mtspr r0,r6,SPR_SR
874 l.nop
875 l.nop
876 l.nop
877 l.nop
878 l.nop
879 l.nop
880 l.nop
881 l.nop
882 l.nop
883 l.nop
885 l.jr r9
886 l.nop
890 l.mfspr r24,r0,SPR_UPR
891 l.andi r26,r24,SPR_UPR_DCP
892 l.sfeq r26,r0
893 l.bf 9f
894 l.nop
897 l.mfspr r6,r0,SPR_SR
898 l.addi r5,r0,-1
899 l.xori r5,r5,SPR_SR_DCE
900 l.and r5,r6,r5
901 l.mtspr r0,r5,SPR_SR
905 If BS=1, 32;
908 l.mfspr r24,r0,SPR_DCCFGR
909 l.andi r26,r24,SPR_DCCFGR_CBS
910 l.srli r28,r26,7
911 l.ori r30,r0,16
912 l.sll r14,r30,r28
918 l.andi r26,r24,SPR_DCCFGR_NCS
919 l.srli r28,r26,3
920 l.ori r30,r0,1
921 l.sll r16,r30,r28
924 l.addi r6,r0,0
925 l.sll r5,r14,r28
926 1:
927 l.mtspr r0,r6,SPR_DCBIR
928 l.sfne r6,r5
929 l.bf 1b
930 l.add r6,r6,r14
933 l.mfspr r6,r0,SPR_SR
934 l.ori r6,r6,SPR_SR_DCE
935 l.mtspr r0,r6,SPR_SR
937 l.jr r9
938 l.nop
979 l.mfspr r6,r0,SPR_ESR_BASE //
980 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
981 l.sfeqi r6,0 // r6 == 0x1 --> SM
982 l.bf exit_with_no_dtranslation //
983 l.nop
996 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
1001 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
1003 l.mfspr r6, r0, SPR_DMMUCFGR
1004 l.andi r6, r6, SPR_DMMUCFGR_NTS
1005 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
1006 l.ori r5, r0, 0x1
1007 l.sll r5, r5, r6 // r5 = number DMMU sets
1008 l.addi r6, r5, -1 // r6 = nsets mask
1009 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1011 l.or r6,r6,r4 // r6 <- r4
1012 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1013 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
1014 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1015 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
1016 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
1020 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
1021 l.bf 1f // goto out
1022 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1025 1:
1026 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1027 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
1028 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1029 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
1030 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
1038 l.rfe // SR <- ESR, PC <- EPC
1044 l.j _dispatch_bus_fault
1075 l.mfspr r6,r0,SPR_ESR_BASE //
1076 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
1077 l.sfeqi r6,0 // r6 == 0x1 --> SM
1078 l.bf exit_with_no_itranslation
1079 l.nop
1083 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
1088 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
1090 l.mfspr r6, r0, SPR_IMMUCFGR
1091 l.andi r6, r6, SPR_IMMUCFGR_NTS
1092 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
1093 l.ori r5, r0, 0x1
1094 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
1095 l.addi r6, r5, -1 // r6 = nsets mask
1096 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1098 l.or r6,r6,r4 // r6 <- r4
1099 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1100 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
1101 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1102 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
1103 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
1113 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
1114 l.bf 1f // goto out
1115 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1118 1:
1119 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1120 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
1121 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1122 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
1123 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
1131 l.rfe // SR <- ESR, PC <- EPC
1136 l.j _dispatch_bus_fault
1137 l.nop
1162 l.mfspr r2,r0,SPR_EEAR_BASE
1167 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1168 l.slli r4,r4,0x2 // to get address << 2
1169 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1175 l.lwz r3,0x0(r4) // get *pmd value
1176 l.sfne r3,r0
1177 l.bnf d_pmd_none
1178 l.addi r3,r0,0xffffe000 // PAGE_MASK
1184 l.lwz r4,0x0(r4) // get **pmd value
1185 l.and r4,r4,r3 // & PAGE_MASK
1186 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1187 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1188 l.slli r3,r3,0x2 // to get address << 2
1189 l.add r3,r3,r4
1190 l.lwz r3,0x0(r3) // this is pte at last
1194 l.andi r4,r3,0x1
1195 l.sfne r4,r0 // is pte present
1196 l.bnf d_pte_not_present
1197 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1201 l.and r4,r3,r4 // apply the mask
1203 l.mfspr r2, r0, SPR_DMMUCFGR
1204 l.andi r2, r2, SPR_DMMUCFGR_NTS
1205 l.srli r2, r2, SPR_DMMUCFGR_NTS_OFF
1206 l.ori r3, r0, 0x1
1207 l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR
1208 l.addi r2, r3, -1 // r2 = nsets mask
1209 l.mfspr r3, r0, SPR_EEAR_BASE
1210 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1211 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1213 l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
1217 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1218 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1219 l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
1224 l.rfe
1240 l.mfspr r2,r0,SPR_EEAR_BASE
1247 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1248 l.slli r4,r4,0x2 // to get address << 2
1249 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1255 l.lwz r3,0x0(r4) // get *pmd value
1256 l.sfne r3,r0
1257 l.bnf i_pmd_none
1258 l.addi r3,r0,0xffffe000 // PAGE_MASK
1265 l.lwz r4,0x0(r4) // get **pmd value
1266 l.and r4,r4,r3 // & PAGE_MASK
1267 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1268 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1269 l.slli r3,r3,0x2 // to get address << 2
1270 l.add r3,r3,r4
1271 l.lwz r3,0x0(r3) // this is pte at last
1276 l.andi r4,r3,0x1
1277 l.sfne r4,r0 // is pte present
1278 l.bnf i_pte_not_present
1279 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1283 l.and r4,r3,r4 // apply the mask
1284 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1285 l.sfeq r3,r0
1286 l.bf itlb_tr_fill //_workaround
1288 l.mfspr r2, r0, SPR_IMMUCFGR
1289 l.andi r2, r2, SPR_IMMUCFGR_NTS
1290 l.srli r2, r2, SPR_IMMUCFGR_NTS_OFF
1291 l.ori r3, r0, 0x1
1292 l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR
1293 l.addi r2, r3, -1 // r2 = nsets mask
1294 l.mfspr r3, r0, SPR_EEAR_BASE
1295 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1296 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1306 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1308 l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
1312 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1313 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1314 l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
1319 l.rfe
1355 l.sw TRAMP_SLOT_0(r3),r4
1356 l.sw TRAMP_SLOT_1(r3),r4
1357 l.sw TRAMP_SLOT_4(r3),r4
1358 l.sw TRAMP_SLOT_5(r3),r4
1361 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1362 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1363 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1364 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1366 l.srli r5,r4,26 // check opcode for write access
1367 l.sfeqi r5,0 // l.j
1368 l.bf 0f
1369 l.sfeqi r5,0x11 // l.jr
1370 l.bf 1f
1371 l.sfeqi r5,1 // l.jal
1372 l.bf 2f
1373 l.sfeqi r5,0x12 // l.jalr
1374 l.bf 3f
1375 l.sfeqi r5,3 // l.bnf
1376 l.bf 4f
1377 l.sfeqi r5,4 // l.bf
1378 l.bf 5f
1380 l.nop
1381 l.j 99b // should never happen
1382 l.nop 1
1391 2: // l.jal
1393 /* 19 20 aa aa l.movhi r9,0xaaaa
1394 * a9 29 bb bb l.ori r9,0xbbbb
1399 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1401 // l.movhi r9,0xaaaa
1402 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1403 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1404 l.srli r5,r6,16
1405 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1407 // l.ori r9,0xbbbb
1408 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1409 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1410 l.andi r5,r6,0xffff
1411 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1416 0: // l.j
1417 l.slli r6,r4,6 // original offset shifted left 6 - 2
1418 // l.srli r6,r6,6 // original offset shifted right 2
1420 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1421 // l.srli r4,r4,6 // old jump position: shifted right 2
1423 l.addi r5,r3,0xc // new jump position (physical)
1424 l.slli r5,r5,4 // new jump position: shifted left 4
1429 l.sub r5,r4,r5 // old_jump - new_jump
1430 l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
1431 l.srli r5,r5,6 // new offset shifted right 2
1434 // l.j has opcode 0x0...
1435 l.sw TRAMP_SLOT_2(r3),r5 // write it back
1437 l.j trampoline_out
1438 l.nop
1442 3: // l.jalr
1444 /* 19 20 aa aa l.movhi r9,0xaaaa
1445 * a9 29 bb bb l.ori r9,0xbbbb
1450 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1452 // l.movhi r9,0xaaaa
1453 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1454 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1455 l.srli r5,r6,16
1456 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1458 // l.ori r9,0xbbbb
1459 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1460 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1461 l.andi r5,r6,0xffff
1462 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1464 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
1465 l.andi r5,r5,0x3ff // clear out opcode part
1466 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1467 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1471 1: // l.jr
1472 l.j trampoline_out
1473 l.nop
1477 4: // l.bnf
1478 5: // l.bf
1479 l.slli r6,r4,6 // original offset shifted left 6 - 2
1480 // l.srli r6,r6,6 // original offset shifted right 2
1482 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1483 // l.srli r4,r4,6 // old jump position: shifted right 2
1485 l.addi r5,r3,0xc // new jump position (physical)
1486 l.slli r5,r5,4 // new jump position: shifted left 4
1491 l.add r6,r6,r4 // (orig_off + old_jump)
1492 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
1493 l.srli r6,r6,6 // new offset shifted right 2
1496 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1497 l.srli r4,r4,16
1498 l.andi r4,r4,0xfc00 // get opcode part
1499 l.slli r4,r4,16
1500 l.or r6,r4,r6 // l.b(n)f new offset
1501 l.sw TRAMP_SLOT_2(r3),r6 // write it back
1503 /* we need to add l.j to EEA + 0x8 */
1505 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1507 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1509 l.slli r4,r4,4 // the amount of info in imediate of jump
1510 l.srli r4,r4,6 // jump instruction with offset
1511 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1518 l.mtspr r0,r5,SPR_EPCR_BASE
1526 If BS=1, 32;
1529 l.mfspr r21,r0,SPR_ICCFGR
1530 l.andi r21,r21,SPR_ICCFGR_CBS
1531 l.srli r21,r21,7
1532 l.ori r23,r0,16
1533 l.sll r14,r23,r21
1535 l.mtspr r0,r5,SPR_ICBIR
1536 l.add r5,r5,r14
1537 l.mtspr r0,r5,SPR_ICBIR
1539 l.jr r9
1540 l.nop
1559 l.lbz r7,0(r3)
1560 l.sfeq r7,r0
1561 l.bf 9f
1562 l.nop
1565 l.movhi r4,hi(UART_BASE_ADD)
1567 l.addi r6,r0,0x20
1568 1: l.lbz r5,5(r4)
1569 l.andi r5,r5,0x20
1570 l.sfeq r5,r6
1571 l.bnf 1b
1572 l.nop
1574 l.sb 0(r4),r7
1576 l.addi r6,r0,0x60
1577 1: l.lbz r5,5(r4)
1578 l.andi r5,r5,0x60
1579 l.sfeq r5,r6
1580 l.bnf 1b
1581 l.nop
1584 l.j 2b
1585 l.addi r3,r3,0x1
1592 l.jr r9
1593 l.nop
1602 l.addi r8,r0,32 // shift register
1604 1: /* remove leading zeros */
1605 l.addi r8,r8,-0x4
1606 l.srl r7,r3,r8
1607 l.andi r7,r7,0xf
1610 l.sfeqi r8,0x4
1611 l.bf 2f
1612 l.nop
1614 l.sfeq r7,r0
1615 l.bf 1b
1616 l.nop
1619 l.srl r7,r3,r8
1621 l.andi r7,r7,0xf
1622 l.sflts r8,r0
1623 l.bf 9f
1625 l.sfgtui r7,0x9
1626 l.bnf 8f
1627 l.nop
1628 l.addi r7,r7,0x27
1631 l.addi r7,r7,0x30
1633 l.movhi r4,hi(UART_BASE_ADD)
1635 l.addi r6,r0,0x20
1636 1: l.lbz r5,5(r4)
1637 l.andi r5,r5,0x20
1638 l.sfeq r5,r6
1639 l.bnf 1b
1640 l.nop
1642 l.sb 0(r4),r7
1644 l.addi r6,r0,0x60
1645 1: l.lbz r5,5(r4)
1646 l.andi r5,r5,0x60
1647 l.sfeq r5,r6
1648 l.bnf 1b
1649 l.nop
1652 l.j 2b
1653 l.addi r8,r8,-0x4
1661 l.jr r9
1662 l.nop
1687 l.movhi r3,hi(UART_BASE_ADD)
1689 l.addi r4,r0,0x7
1690 l.sb 0x2(r3),r4
1692 l.addi r4,r0,0x0
1693 l.sb 0x1(r3),r4
1695 l.addi r4,r0,0x3
1696 l.sb 0x3(r3),r4
1698 l.lbz r5,3(r3)
1699 l.ori r4,r5,0x80
1700 l.sb 0x3(r3),r4
1701 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1702 l.sb UART_DLM(r3),r4
1703 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1704 l.sb UART_DLL(r3),r4
1705 l.sb 0x3(r3),r5
1707 l.jr r9
1708 l.nop
1716 l.ori r3,r0,SPR_SR_SM
1717 l.mtspr r0,r3,SPR_ESR_BASE
1718 l.rfe