39 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_enable()  local
43 		 __func__, gck->gckdiv, gck->parent_id);  in clk_generated_enable()
45 	spin_lock_irqsave(gck->lock, flags);  in clk_generated_enable()
46 	regmap_write(gck->regmap, gck->layout->offset,  in clk_generated_enable()
47 		     (gck->id & gck->layout->pid_mask));  in clk_generated_enable()
48 	regmap_update_bits(gck->regmap, gck->layout->offset,  in clk_generated_enable()
49 			   AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |  in clk_generated_enable()
50 			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,  in clk_generated_enable()
51 			   field_prep(gck->layout->gckcss_mask, gck->parent_id) |  in clk_generated_enable()
52 			   gck->layout->cmd |  in clk_generated_enable()
53 			   FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |  in clk_generated_enable()
55 	spin_unlock_irqrestore(gck->lock, flags);  in clk_generated_enable()
61 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_disable()  local
64 	spin_lock_irqsave(gck->lock, flags);  in clk_generated_disable()
65 	regmap_write(gck->regmap, gck->layout->offset,  in clk_generated_disable()
66 		     (gck->id & gck->layout->pid_mask));  in clk_generated_disable()
67 	regmap_update_bits(gck->regmap, gck->layout->offset,  in clk_generated_disable()
68 			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,  in clk_generated_disable()
69 			   gck->layout->cmd);  in clk_generated_disable()
70 	spin_unlock_irqrestore(gck->lock, flags);  in clk_generated_disable()
75 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_is_enabled()  local
79 	spin_lock_irqsave(gck->lock, flags);  in clk_generated_is_enabled()
80 	regmap_write(gck->regmap, gck->layout->offset,  in clk_generated_is_enabled()
81 		     (gck->id & gck->layout->pid_mask));  in clk_generated_is_enabled()
82 	regmap_read(gck->regmap, gck->layout->offset, &status);  in clk_generated_is_enabled()
83 	spin_unlock_irqrestore(gck->lock, flags);  in clk_generated_is_enabled()
92 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_recalc_rate()  local
94 	return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);  in clk_generated_recalc_rate()
126 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_determine_rate()  local
136 	if (gck->range.max && req->rate > gck->range.max)  in clk_generated_determine_rate()
137 		req->rate = gck->range.max;  in clk_generated_determine_rate()
138 	if (gck->range.min && req->rate < gck->range.min)  in clk_generated_determine_rate()
139 		req->rate = gck->range.min;  in clk_generated_determine_rate()
142 		if (gck->chg_pid == i)  in clk_generated_determine_rate()
152 		    (gck->range.max && min_rate > gck->range.max))  in clk_generated_determine_rate()
173 	 * that the only clks able to modify gck rate are those of audio IPs.  in clk_generated_determine_rate()
176 	if (gck->chg_pid < 0)  in clk_generated_determine_rate()
179 	parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);  in clk_generated_determine_rate()
200 	if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))  in clk_generated_determine_rate()
210 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_set_parent()  local
215 	if (gck->mux_table)  in clk_generated_set_parent()
216 		gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);  in clk_generated_set_parent()
218 		gck->parent_id = index;  in clk_generated_set_parent()
225 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_get_parent()  local
227 	return gck->parent_id;  in clk_generated_get_parent()
235 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_set_rate()  local
241 	if (gck->range.max && rate > gck->range.max)  in clk_generated_set_rate()
248 	gck->gckdiv = div - 1;  in clk_generated_set_rate()
267  * @gck:	Generated clock to set the startup parameters for.
272 static void clk_generated_startup(struct clk_generated *gck)  in clk_generated_startup()  argument
277 	spin_lock_irqsave(gck->lock, flags);  in clk_generated_startup()
278 	regmap_write(gck->regmap, gck->layout->offset,  in clk_generated_startup()
279 		     (gck->id & gck->layout->pid_mask));  in clk_generated_startup()
280 	regmap_read(gck->regmap, gck->layout->offset, &tmp);  in clk_generated_startup()
281 	spin_unlock_irqrestore(gck->lock, flags);  in clk_generated_startup()
283 	gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);  in clk_generated_startup()
284 	gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);  in clk_generated_startup()
295 	struct clk_generated *gck;  in at91_clk_register_generated()  local
300 	gck = kzalloc(sizeof(*gck), GFP_KERNEL);  in at91_clk_register_generated()
301 	if (!gck)  in at91_clk_register_generated()
312 	gck->id = id;  in at91_clk_register_generated()
313 	gck->hw.init = &init;  in at91_clk_register_generated()
314 	gck->regmap = regmap;  in at91_clk_register_generated()
315 	gck->lock = lock;  in at91_clk_register_generated()
316 	gck->range = *range;  in at91_clk_register_generated()
317 	gck->chg_pid = chg_pid;  in at91_clk_register_generated()
318 	gck->layout = layout;  in at91_clk_register_generated()
319 	gck->mux_table = mux_table;  in at91_clk_register_generated()
321 	clk_generated_startup(gck);  in at91_clk_register_generated()
322 	hw = &gck->hw;  in at91_clk_register_generated()
323 	ret = clk_hw_register(NULL, &gck->hw);  in at91_clk_register_generated()
325 		kfree(gck);  in at91_clk_register_generated()