57 	struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];  member
827 	u32 clksel;  in mux_set_parent()  local
832 	clksel = hwc->parent_to_clksel[idx];  in mux_set_parent()
833 	cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);  in mux_set_parent()
841 	u32 clksel;  in mux_get_parent()  local
844 	clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;  in mux_get_parent()
846 	ret = hwc->clksel_to_parent[clksel];  in mux_get_parent()
848 		pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);  in mux_get_parent()
874 	if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))  in get_pll_div()
877 	pll = hwc->info->clksel[idx].pll;  in get_pll_div()
878 	div = hwc->info->clksel[idx].div;  in get_pll_div()
911 		if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&  in create_mux_common()
950 	u32 clksel;  in create_one_cmux()  local
964 	 * Find the rate for the default clksel, and treat it as the  in create_one_cmux()
967 	 * default clksel) may be inappropriately excluded on certain  in create_one_cmux()
970 	clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;  in create_one_cmux()
971 	div = get_pll_div(cg, hwc, clksel);  in create_one_cmux()