1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
18 #include "axg-audio.h"
19 #include "clk-regmap.h"
20 #include "clk-phase.h"
21 #include "sclk-div.h"
229 	{ .name = "aud_mst_a_sclk", .index = -1, },
230 	{ .name = "aud_mst_b_sclk", .index = -1, },
231 	{ .name = "aud_mst_c_sclk", .index = -1, },
232 	{ .name = "aud_mst_d_sclk", .index = -1, },
233 	{ .name = "aud_mst_e_sclk", .index = -1, },
234 	{ .name = "aud_mst_f_sclk", .index = -1, },
249 	{ .name = "aud_mst_a_lrclk", .index = -1, },
250 	{ .name = "aud_mst_b_lrclk", .index = -1, },
251 	{ .name = "aud_mst_c_lrclk", .index = -1, },
252 	{ .name = "aud_mst_d_lrclk", .index = -1, },
253 	{ .name = "aud_mst_e_lrclk", .index = -1, },
254 	{ .name = "aud_mst_f_lrclk", .index = -1, },
291 	{ .name = "aud_mst_a_mclk", .index = -1,  },
292 	{ .name = "aud_mst_b_mclk", .index = -1,  },
293 	{ .name = "aud_mst_c_mclk", .index = -1,  },
294 	{ .name = "aud_mst_d_mclk", .index = -1,  },
295 	{ .name = "aud_mst_e_mclk", .index = -1,  },
296 	{ .name = "aud_mst_f_mclk", .index = -1,  },
301 	{ .name = "aud_mst_a_sclk", .index = -1, },
302 	{ .name = "aud_mst_b_sclk", .index = -1, },
303 	{ .name = "aud_mst_c_sclk", .index = -1, },
304 	{ .name = "aud_mst_d_sclk", .index = -1, },
305 	{ .name = "aud_mst_e_sclk", .index = -1, },
306 	{ .name = "aud_mst_f_sclk", .index = -1, },
311 	{ .name = "aud_mst_a_lrclk", .index = -1, },
312 	{ .name = "aud_mst_b_lrclk", .index = -1, },
313 	{ .name = "aud_mst_c_lrclk", .index = -1, },
314 	{ .name = "aud_mst_d_lrclk", .index = -1, },
315 	{ .name = "aud_mst_e_lrclk", .index = -1, },
316 	{ .name = "aud_mst_f_lrclk", .index = -1, },
326 static struct clk_regmap pdm =  variable
327 	AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1);
545 /* AXG Clocks */
553 /* AXG/G12A Clocks */
556 		/* Provide aud_top signal name on axg and g12a */
817 		[AUD_CLKID_PDM]			= &pdm.hw,
950 		[AUD_CLKID_PDM]			= &pdm.hw,
1095 		[AUD_CLKID_PDM]			= &pdm.hw,
1250 	&pdm,
1374 	&pdm,
1512 	&pdm,
1668 		if (ret != -EPROBE_DEFER)  in devm_clk_get_enable()
1701 	unsigned int stride = regmap_get_reg_stride(rst->map);  in axg_audio_reset_reg_and_bit()
1704 	*reg += rst->offset;  in axg_audio_reset_reg_and_bit()
1717 	regmap_update_bits(rst->map, offset, BIT(bit),  in axg_audio_reset_update()
1732 	regmap_read(rst->map, offset, &val);  in axg_audio_reset_status()
1785 	struct device *dev = &pdev->dev;  in axg_audio_clkc_probe()
1795 		return -EINVAL;  in axg_audio_clkc_probe()
1819 	for (i = 0; i < data->regmap_clk_num; i++)  in axg_audio_clkc_probe()
1820 		data->regmap_clks[i]->map = map;  in axg_audio_clkc_probe()
1823 	for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {  in axg_audio_clkc_probe()
1826 		hw = data->hw_onecell_data->hws[i];  in axg_audio_clkc_probe()
1831 		name = hw->init->name;  in axg_audio_clkc_probe()
1841 					data->hw_onecell_data);  in axg_audio_clkc_probe()
1846 	if (!data->reset_num)  in axg_audio_clkc_probe()
1851 		return -ENOMEM;  in axg_audio_clkc_probe()
1853 	rst->map = map;  in axg_audio_clkc_probe()
1854 	rst->offset = data->reset_offset;  in axg_audio_clkc_probe()
1855 	rst->rstc.nr_resets = data->reset_num;  in axg_audio_clkc_probe()
1856 	rst->rstc.ops = &axg_audio_rstc_ops;  in axg_audio_clkc_probe()
1857 	rst->rstc.of_node = dev->of_node;  in axg_audio_clkc_probe()
1858 	rst->rstc.owner = THIS_MODULE;  in axg_audio_clkc_probe()
1860 	return devm_reset_controller_register(dev, &rst->rstc);  in axg_audio_clkc_probe()
1887 		.compatible = "amlogic,axg-audio-clkc",
1890 		.compatible = "amlogic,g12a-audio-clkc",
1893 		.compatible = "amlogic,sm1-audio-clkc",
1902 		.name	= "axg-audio-clkc",
1908 MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver");