Lines Matching +full:0 +full:x12010
81 { P_XO, 0 },
93 { P_XO, 0 },
103 { P_XO, 0 },
113 { P_XO, 0 },
125 { P_XO, 0 },
135 { P_XO, 0 },
145 { P_XO, 0 },
155 { P_XO, 0 },
175 F(48000000, P_XO, 1, 0, 0),
176 F(200000000, P_FEPLL200, 1, 0, 0),
181 .cmd_rcgr = 0x1b000,
195 .halt_reg = 0x1b010,
197 .enable_reg = 0x1b010,
198 .enable_mask = BIT(0),
212 .halt_reg = 0x1b00C,
214 .enable_reg = 0x1b00C,
215 .enable_mask = BIT(0),
234 .cmd_rcgr = 0x200c,
247 .halt_reg = 0x2008,
249 .enable_reg = 0x2008,
250 .enable_mask = BIT(0),
264 .cmd_rcgr = 0x3000,
277 .halt_reg = 0x3010,
279 .enable_reg = 0x3010,
280 .enable_mask = BIT(0),
300 F(48000000, P_XO, 1, 0, 0),
305 .cmd_rcgr = 0x2024,
319 .halt_reg = 0x2004,
321 .enable_reg = 0x2004,
322 .enable_mask = BIT(0),
336 .cmd_rcgr = 0x3014,
350 .halt_reg = 0x300c,
352 .enable_reg = 0x300c,
353 .enable_mask = BIT(0),
376 F(48000000, P_XO, 1, 0, 0),
381 .cmd_rcgr = 0x2044,
395 .halt_reg = 0x203c,
397 .enable_reg = 0x203c,
398 .enable_mask = BIT(0),
412 .cmd_rcgr = 0x3034,
426 .halt_reg = 0x302c,
428 .enable_reg = 0x302c,
429 .enable_mask = BIT(0),
443 F(1250000, P_FEPLL200, 1, 16, 0),
444 F(2500000, P_FEPLL200, 1, 8, 0),
445 F(5000000, P_FEPLL200, 1, 4, 0),
450 .cmd_rcgr = 0x8004,
464 .halt_reg = 0x8000,
466 .enable_reg = 0x8000,
467 .enable_mask = BIT(0),
481 .cmd_rcgr = 0x9004,
495 .halt_reg = 0x9000,
497 .enable_reg = 0x9000,
498 .enable_mask = BIT(0),
512 .cmd_rcgr = 0xa004,
526 .halt_reg = 0xa000,
528 .enable_reg = 0xa000,
529 .enable_mask = BIT(0),
544 F(400000, P_XO, 1, 1, 0),
549 F(192000000, P_DDRPLL, 1, 0, 0),
554 .cmd_rcgr = 0x18004,
568 F(48000000, P_XO, 1, 0, 0),
569 F(200000000, P_FEPLL200, 1, 0, 0),
570 F(384000000, P_DDRPLLAPSS, 1, 0, 0),
571 F(413000000, P_DDRPLLAPSS, 1, 0, 0),
572 F(448000000, P_DDRPLLAPSS, 1, 0, 0),
573 F(488000000, P_DDRPLLAPSS, 1, 0, 0),
574 F(500000000, P_FEPLL500, 1, 0, 0),
575 F(512000000, P_DDRPLLAPSS, 1, 0, 0),
576 F(537000000, P_DDRPLLAPSS, 1, 0, 0),
577 F(565000000, P_DDRPLLAPSS, 1, 0, 0),
578 F(597000000, P_DDRPLLAPSS, 1, 0, 0),
579 F(632000000, P_DDRPLLAPSS, 1, 0, 0),
580 F(672000000, P_DDRPLLAPSS, 1, 0, 0),
581 F(716000000, P_DDRPLLAPSS, 1, 0, 0),
586 .cmd_rcgr = 0x1900c,
600 F(48000000, P_XO, 1, 0, 0),
601 F(100000000, P_FEPLL200, 2, 0, 0),
606 .cmd_rcgr = 0x19014,
619 .halt_reg = 0x19004,
622 .enable_reg = 0x6000,
637 .halt_reg = 0x1008,
640 .enable_reg = 0x6000,
654 .halt_reg = 0x2103c,
656 .enable_reg = 0x2103c,
657 .enable_mask = BIT(0),
670 .halt_reg = 0x1300c,
672 .enable_reg = 0x1300c,
673 .enable_mask = BIT(0),
687 .halt_reg = 0x16024,
690 .enable_reg = 0x6000,
691 .enable_mask = BIT(0),
704 .halt_reg = 0x16020,
707 .enable_reg = 0x6000,
721 .halt_reg = 0x1601c,
724 .enable_reg = 0x6000,
738 .halt_reg = 0x12010,
740 .enable_reg = 0x12010,
741 .enable_mask = BIT(0),
755 .halt_reg = 0xe004,
758 .enable_reg = 0x6000,
772 .halt_reg = 0xe008,
774 .enable_reg = 0xe008,
775 .enable_mask = BIT(0),
788 .halt_reg = 0x1d00c,
790 .enable_reg = 0x1d00c,
791 .enable_mask = BIT(0),
804 .halt_reg = 0x1d004,
806 .enable_reg = 0x1d004,
807 .enable_mask = BIT(0),
820 .halt_reg = 0x1d008,
822 .enable_reg = 0x1d008,
823 .enable_mask = BIT(0),
836 .halt_reg = 0x13004,
839 .enable_reg = 0x6000,
853 .halt_reg = 0x1c008,
855 .enable_reg = 0x1c008,
856 .enable_mask = BIT(0),
869 .halt_reg = 0x1c004,
871 .enable_reg = 0x1c004,
872 .enable_mask = BIT(0),
885 .halt_reg = 0x18010,
887 .enable_reg = 0x18010,
888 .enable_mask = BIT(0),
901 .halt_reg = 0x1800c,
903 .enable_reg = 0x1800c,
904 .enable_mask = BIT(0),
918 .halt_reg = 0x5004,
921 .enable_reg = 0x6000,
935 .halt_reg = 0x1e00c,
937 .enable_reg = 0x1e00c,
938 .enable_mask = BIT(0),
951 .halt_reg = 0x1e010,
953 .enable_reg = 0x1e010,
954 .enable_mask = BIT(0),
967 .halt_reg = 0x1e014,
969 .enable_reg = 0x1e014,
970 .enable_mask = BIT(0),
984 F(2000000, P_FEPLL200, 10, 0, 0),
989 .cmd_rcgr = 0x1e000,
1002 .halt_reg = 0x1e028,
1004 .enable_reg = 0x1e028,
1005 .enable_mask = BIT(0),
1018 .halt_reg = 0x1e02C,
1020 .enable_reg = 0x1e02C,
1021 .enable_mask = BIT(0),
1034 .halt_reg = 0x1e030,
1036 .enable_reg = 0x1e030,
1037 .enable_mask = BIT(0),
1051 F(125000000, P_FEPLL125DLY, 1, 0, 0),
1056 .cmd_rcgr = 0x12000,
1070 F(48000000, P_XO, 1, 0, 0),
1071 F(250000000, P_FEPLLWCSS2G, 1, 0, 0),
1076 .cmd_rcgr = 0x1f000,
1090 .halt_reg = 0x1f00C,
1092 .enable_reg = 0x1f00C,
1093 .enable_mask = BIT(0),
1107 .halt_reg = 0x1f00C,
1109 .enable_reg = 0x1f00C,
1110 .enable_mask = BIT(0),
1124 .halt_reg = 0x1f010,
1126 .enable_reg = 0x1f010,
1127 .enable_mask = BIT(0),
1140 F(48000000, P_XO, 1, 0, 0),
1141 F(250000000, P_FEPLLWCSS5G, 1, 0, 0),
1146 .cmd_rcgr = 0x20000,
1159 .halt_reg = 0x2000c,
1161 .enable_reg = 0x2000c,
1162 .enable_mask = BIT(0),
1176 .halt_reg = 0x2000c,
1178 .enable_reg = 0x2000c,
1179 .enable_mask = BIT(0),
1193 .halt_reg = 0x20010,
1195 .enable_reg = 0x20010,
1196 .enable_mask = BIT(0),
1235 .reg = 0x2e020,
1243 .reg = 0x2f020,
1295 return 0; in clk_cpu_div_set_rate()
1338 { 384000000, P_XO, 0xd, 0, 0 },
1339 { 413000000, P_XO, 0xc, 0, 0 },
1340 { 448000000, P_XO, 0xb, 0, 0 },
1341 { 488000000, P_XO, 0xa, 0, 0 },
1342 { 512000000, P_XO, 0x9, 0, 0 },
1343 { 537000000, P_XO, 0x8, 0, 0 },
1344 { 565000000, P_XO, 0x7, 0, 0 },
1345 { 597000000, P_XO, 0x6, 0, 0 },
1346 { 632000000, P_XO, 0x5, 0, 0 },
1347 { 672000000, P_XO, 0x4, 0, 0 },
1348 { 716000000, P_XO, 0x3, 0, 0 },
1349 { 768000000, P_XO, 0x2, 0, 0 },
1350 { 823000000, P_XO, 0x1, 0, 0 },
1351 { 896000000, P_XO, 0x0, 0, 0 },
1356 .cdiv.reg = 0x2e020,
1360 .enable_reg = 0x2e000,
1361 .enable_mask = BIT(0),
1487 { 0, 15 },
1495 .cdiv.reg = 0x2f020,
1513 .cdiv.reg = 0x2f020,
1531 F(48000000, P_XO, 1, 0, 0),
1532 F(100000000, P_FEPLL200, 2, 0, 0),
1537 .cmd_rcgr = 0x21024,
1550 .halt_reg = 0x21030,
1552 .enable_reg = 0x21030,
1553 .enable_mask = BIT(0),
1640 [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
1641 [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
1642 [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
1643 [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
1644 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
1645 [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
1646 [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
1647 [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
1648 [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
1649 [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
1650 [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
1651 [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
1652 [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
1653 [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
1654 [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
1655 [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
1656 [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
1657 [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
1658 [PCIE_AHB_ARES] = { 0x1d010, 10 },
1659 [PCIE_PWR_ARES] = { 0x1d010, 9 },
1660 [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
1661 [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
1662 [PCIE_PHY_ARES] = { 0x1d010, 6 },
1663 [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
1664 [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
1665 [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
1666 [PCIE_PIPE_ARES] = { 0x1d010, 2 },
1667 [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
1668 [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
1669 [ESS_RESET] = { 0x12008, 0},
1670 [GCC_BLSP1_BCR] = {0x01000, 0},
1671 [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
1672 [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
1673 [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
1674 [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
1675 [GCC_BIMC_BCR] = {0x04000, 0},
1676 [GCC_TLMM_BCR] = {0x05000, 0},
1677 [GCC_IMEM_BCR] = {0x0E000, 0},
1678 [GCC_ESS_BCR] = {0x12008, 0},
1679 [GCC_PRNG_BCR] = {0x13000, 0},
1680 [GCC_BOOT_ROM_BCR] = {0x13008, 0},
1681 [GCC_CRYPTO_BCR] = {0x16000, 0},
1682 [GCC_SDCC1_BCR] = {0x18000, 0},
1683 [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
1684 [GCC_AUDIO_BCR] = {0x1B008, 0},
1685 [GCC_QPIC_BCR] = {0x1C000, 0},
1686 [GCC_PCIE_BCR] = {0x1D000, 0},
1687 [GCC_USB2_BCR] = {0x1E008, 0},
1688 [GCC_USB2_PHY_BCR] = {0x1E018, 0},
1689 [GCC_USB3_BCR] = {0x1E024, 0},
1690 [GCC_USB3_PHY_BCR] = {0x1E034, 0},
1691 [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
1692 [GCC_PCNOC_BCR] = {0x2102C, 0},
1693 [GCC_DCD_BCR] = {0x21038, 0},
1694 [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
1695 [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
1696 [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
1697 [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
1698 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
1699 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
1700 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
1701 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
1702 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
1703 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
1704 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
1705 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
1706 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
1707 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
1708 [GCC_TCSR_BCR] = {0x22000, 0},
1709 [GCC_MPM_BCR] = {0x24000, 0},
1710 [GCC_SPDM_BCR] = {0x25000, 0},
1717 .max_register = 0x2ffff,
1739 int err = 0; in gcc_ipq4019_cpu_clk_notifier_fn()