12  * the HVS at that timing, and feeds it to the encoder.
16  * responsible for writing the display list for the HVS channel that
106 	 * pixelvalve by the HVS, and also the scaler status.  in vc4_crtc_get_scanout_position()
116 	/* Vertical position of hvs composed scanline. */  in vc4_crtc_get_scanout_position()
129 	/* This is the offset we need for translating hvs -> pv scanout pos. */  in vc4_crtc_get_scanout_position()
135 	/* HVS more than fifo_lines into frame for compositing? */  in vc4_crtc_get_scanout_position()
139 		 * from HVS. The actual PV scanout can not trail behind more  in vc4_crtc_get_scanout_position()
141 		 * in active scanout the HVS and PV work in lockstep wrt. HVS  in vc4_crtc_get_scanout_position()
144 		 * fifo, the HVS will immediately refill it, therefore  in vc4_crtc_get_scanout_position()
145 		 * incrementing vpos. Therefore we choose HVS read position -  in vc4_crtc_get_scanout_position()
155 	 * Less: This happens when we are in vblank and the HVS, after getting  in vc4_crtc_get_scanout_position()
159 	 * the fifo, so the fifo will be full quickly and the HVS has to pause.  in vc4_crtc_get_scanout_position()
183 		 * If the HVS fifo is not yet full then we know for certain  in vc4_crtc_get_scanout_position()
184 		 * we are at the very beginning of vblank, as the hvs just  in vc4_crtc_get_scanout_position()
217 	 * Pixels are pulled from the HVS if the number of bytes is  in vc4_get_fifo_full_level()
245 		 * set) and stall the HVS / PV, eventually resulting in  in vc4_get_fifo_full_level()
255 		if (!vc4->hvs->hvs5)  in vc4_get_fifo_full_level()
394 	if (vc4->hvs->hvs5)  in vc4_crtc_config_pv()
662 		 * happens, the HVS will be using the previous display list with  in vc4_crtc_handle_page_flip()
863 		spin_lock_irqsave(&vc4->hvs->mm_lock, flags);  in vc4_crtc_destroy_state()
865 		spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);  in vc4_crtc_destroy_state()
1086 	if (!vc4->hvs->hvs5) {  in vc4_crtc_init()