46  *	bit1 1=legacy_compatible_mode, 0=native_pci_mode
47  *	bit0 1=test_mode, 0=normal(default)
51  *	bit1 channel0 busmaster interrupt status 0=none, 1=asserted
52  *	bit0 channel0 interrupt status 0=none, 1=asserted
56  *	bit4 legacy_header: 1=present, 0=absent
57  *	bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
58  *	bit2 channel1 interrupt status 0=none, 1=asserted (read only)
59  *	bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
60  *	bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
63  *	bit7 1=autoincrement CPR bits 2-0 after each access of CDR
64  *	bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
65  *	bit5 0=enabled master burst access (default), 1=disable  (write only)
66  *	bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
67  *	bit3 0=primary IDE channel, 1=secondary IDE channel
68  *	bits2-0 register index for accesses through CDR port
70  * trm290_base+0 "CDR" Config Data Register (word)
72  *	selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
75  * Index-0 Base address register for command block (word)
76  *	defaults: 0x1f0 for primary, 0x170 for secondary
79  *	bit7 1=DMA enable, 0=DMA disable
80  *	bit6 1=activate IDE_RESET, 0=no action (default)
81  *	bit5 1=enable IORDY, 0=disable IORDY (default)
82  *	bit4 0=16-bit data port(default), 1=8-bit (XT) data port
83  *	bit3 interrupt polarity: 1=active_low, 0=active_high(default)
84  *	bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
85  *	bit1 bus_master_mode(?): 1=enable, 0=disable(default)
86  *	bit0 enable_io_ports: 1=enable(default), 0=disable
88  * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
89  *	bits7-0 bits7-0 of readahead count
92  *	bit7 1=enable_readahead, 0=disable_readahead(default)
93  *	bit6 1=clear_FIFO, 0=no_action
95  *	bit4 mode4 timing control: 1=enable, 0=disable(default)
98  *	bits1-0 bits9-8 of read-ahead count
101  *	defaults: 0x3f6 for primary, 0x376 for secondary
104  *	standard PCI "clk" (clock) counts, default value = 0xf5
110  *	bits2-0 active time:	000=2clk, 001=3clk, 010=4clk,
115  *	same layout as Index-5, default value = 0xde
118  *	0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde	; primary
119  *	0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde	; secondary
122  *	0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde	; primary
123  *	0x0170,0x21,0xff,0x80,0x0376,0x09,0xde	; secondary
126  *	0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde	; primary
127  *	0x0170,0x21,0xff,0x80,0x0376,0x00,0xde	; secondary
148 	u16 reg = 0;  in trm290_prepare_drive()
152 	reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);  in trm290_prepare_drive()
159 		outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);  in trm290_prepare_drive()
160 		outw(reg & 0xff, hwif->config_data);  in trm290_prepare_drive()
166 		reg &= 0x13;  in trm290_prepare_drive()
189 	return 0;  in trm290_dma_check()
198 	if (count == 0)  in trm290_dma_setup()
206 	return 0;  in trm290_dma_setup()
218 	trm290_prepare_drive(drive, 0);  in trm290_dma_end()
220 	return status != 0x00ff;  in trm290_dma_end()
227 	return status == 0x00ff;  in trm290_dma_test_irq()
239 	u8 reg = 0;  in init_hwif_trm290()
244 		cfg_base = 0x3df0;  in init_hwif_trm290()
247 	printk(KERN_CONT " config base at 0x%04x\n", cfg_base);  in init_hwif_trm290()
249 	hwif->dma_base = (cfg_base + 4) ^ (hwif->channel ? 0x80 : 0);  in init_hwif_trm290()
251 	printk(KERN_INFO "    %s: BM-DMA at 0x%04lx-0x%04lx\n",  in init_hwif_trm290()
259 	outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);  in init_hwif_trm290()
261 	hwif->select_data = 0x21;  in init_hwif_trm290()
266 	reg = (reg & 0x10) | 0x03;  in init_hwif_trm290()
270 	if (reg & 0x10)  in init_hwif_trm290()
281 		u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;  in init_hwif_trm290()
282 		static u16 next_offset = 0;  in init_hwif_trm290()
285 		outb(0x54 | (hwif->channel << 3), hwif->config_data + 1);  in init_hwif_trm290()
289 		if (old != compat && old_mask == 0xff) {  in init_hwif_trm290()
291 			compat += (next_offset += 0x400);  in init_hwif_trm290()
296 				"old=0x%04x, new=0x%04x\n",  in init_hwif_trm290()
334 #if 0 /* play it safe for now */
347 	{ PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290), 0 },
348 	{ 0, },