Lines Matching +full:wakeup +full:- +full:threshold

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
64 	/* duty cycle, 0-100 */
67 	/* hw-specific operation function pointers; most of these must be
137 /* low-speed carrier frequency limits (Hz) */
141 /* high-speed carrier frequency limits (Hz) */
153  * n in RDCR produces a tolerance of +/- n * 6.25% around the center
158  * frequency A = (H - L) / (H + L). We can use this in order to honor the
159  * s_rx_carrier_range() call in ir-core. We'll suppose that any request
194  * (EC - LPC I/O)
225 #define IT87_HCFS	0x40	/* high-speed carrier frequency select */
233 #define IT87_FIFOTL	0x30	/* FIFO level threshold mask */
234 #define IT87_FIFOTL_DEFAULT 0x20	/* FIFO level threshold default
235 					 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
236 					 * 0x30 -> 25 */
251 #define IT87_RXFTO	0x80	/* receiver FIFO time-out */
292 #define IT85_C0WCL	0x0d	/* wakeup code length register */
293 #define IT85_C0WCR	0x0e	/* wakeup code read/write register */
294 #define IT85_C0WPS	0x0f	/* wakeup power control/status register */
301 #define IT85_FIFOTL	0x0c	/* FIFO level threshold mask */
302 #define IT85_FIFOTL_DEFAULT 0x08	/* FIFO level threshold default
303 					 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
304 					 * 0x0c -> 25 */
352 #define IT85_RXFTO	0x80	/* receiver FIFO time-out */
355 #define IT85_WCL	0x3f	/* wakeup code length mask */
361 #define IT85_RCRST	0x10	/* wakeup code reading counter reset bit */
362 #define IT85_WCRST	0x20	/* wakeup code writing counter reset bit */
372  * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
373  * selectable by a single bank-select bit that's mapped onto both banks. The
376  * reserved high-order bit are placed at the same offset in both banks in
405 #define IT8708_C0WCL	0x05	/* wakeup code length register */
406 #define IT8708_C0WCR	0x06	/* wakeup code read/write register */
407 #define IT8708_C0WPS	0x07	/* wakeup power control/status register */
431  * a specific firmware running on the IT8512's embedded micro-controller.
432  * In addition of the embedded micro-controller, the IT8512 chip contains a
435  * micro-controller. The CIR module is only accessible by the
436  * micro-controller.
438  * The battery-backed SRAM module is accessible by the host CPU and the
439  * micro-controller. So one of the MC's firmware role is to act as a bridge
443  * communication protocol is not, so it was reverse-engineered.