Lines Matching +full:0 +full:x0140000
22 REG(ANA_ADVLEARN, 0x0089a0),
23 REG(ANA_VLANMASK, 0x0089a4),
25 REG(ANA_ANAGEFIL, 0x0089ac),
26 REG(ANA_ANEVENTS, 0x0089b0),
27 REG(ANA_STORMLIMIT_BURST, 0x0089b4),
28 REG(ANA_STORMLIMIT_CFG, 0x0089b8),
29 REG(ANA_ISOLATED_PORTS, 0x0089c8),
30 REG(ANA_COMMUNITY_PORTS, 0x0089cc),
31 REG(ANA_AUTOAGE, 0x0089d0),
32 REG(ANA_MACTOPTIONS, 0x0089d4),
33 REG(ANA_LEARNDISC, 0x0089d8),
34 REG(ANA_AGENCTRL, 0x0089dc),
35 REG(ANA_MIRRORPORTS, 0x0089e0),
36 REG(ANA_EMIRRORPORTS, 0x0089e4),
37 REG(ANA_FLOODING, 0x0089e8),
38 REG(ANA_FLOODING_IPMC, 0x008a08),
39 REG(ANA_SFLOW_CFG, 0x008a0c),
40 REG(ANA_PORT_MODE, 0x008a28),
41 REG(ANA_CUT_THRU_CFG, 0x008a48),
42 REG(ANA_PGID_PGID, 0x008400),
43 REG(ANA_TABLES_ANMOVED, 0x007f1c),
44 REG(ANA_TABLES_MACHDATA, 0x007f20),
45 REG(ANA_TABLES_MACLDATA, 0x007f24),
46 REG(ANA_TABLES_STREAMDATA, 0x007f28),
47 REG(ANA_TABLES_MACACCESS, 0x007f2c),
48 REG(ANA_TABLES_MACTINDX, 0x007f30),
49 REG(ANA_TABLES_VLANACCESS, 0x007f34),
50 REG(ANA_TABLES_VLANTIDX, 0x007f38),
51 REG(ANA_TABLES_ISDXACCESS, 0x007f3c),
52 REG(ANA_TABLES_ISDXTIDX, 0x007f40),
53 REG(ANA_TABLES_ENTRYLIM, 0x007f00),
54 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44),
55 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48),
56 REG(ANA_TABLES_STREAMACCESS, 0x007f4c),
57 REG(ANA_TABLES_STREAMTIDX, 0x007f50),
58 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54),
59 REG(ANA_TABLES_SEQ_MASK, 0x007f58),
60 REG(ANA_TABLES_SFID_MASK, 0x007f5c),
61 REG(ANA_TABLES_SFIDACCESS, 0x007f60),
62 REG(ANA_TABLES_SFIDTIDX, 0x007f64),
63 REG(ANA_MSTI_STATE, 0x008600),
64 REG(ANA_OAM_UPM_LM_CNT, 0x008000),
65 REG(ANA_SG_ACCESS_CTRL, 0x008a64),
66 REG(ANA_SG_CONFIG_REG_1, 0x007fb0),
67 REG(ANA_SG_CONFIG_REG_2, 0x007fb4),
68 REG(ANA_SG_CONFIG_REG_3, 0x007fb8),
69 REG(ANA_SG_CONFIG_REG_4, 0x007fbc),
70 REG(ANA_SG_CONFIG_REG_5, 0x007fc0),
71 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80),
72 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90),
73 REG(ANA_SG_STATUS_REG_1, 0x008980),
74 REG(ANA_SG_STATUS_REG_2, 0x008984),
75 REG(ANA_SG_STATUS_REG_3, 0x008988),
76 REG(ANA_PORT_VLAN_CFG, 0x007800),
77 REG(ANA_PORT_DROP_CFG, 0x007804),
78 REG(ANA_PORT_QOS_CFG, 0x007808),
79 REG(ANA_PORT_VCAP_CFG, 0x00780c),
80 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810),
81 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c),
82 REG(ANA_PORT_PCP_DEI_MAP, 0x007820),
83 REG(ANA_PORT_CPU_FWD_CFG, 0x007860),
84 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864),
85 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868),
86 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c),
87 REG(ANA_PORT_PORT_CFG, 0x007870),
88 REG(ANA_PORT_POL_CFG, 0x007874),
89 REG(ANA_PORT_PTP_CFG, 0x007878),
90 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c),
91 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880),
92 REG(ANA_PORT_SFID_CFG, 0x007884),
93 REG(ANA_PFC_PFC_CFG, 0x008800),
99 REG(ANA_AGGR_CFG, 0x008a68),
100 REG(ANA_CPUQ_CFG, 0x008a6c),
102 REG(ANA_CPUQ_8021_CFG, 0x008a74),
103 REG(ANA_DSCP_CFG, 0x008ab4),
104 REG(ANA_DSCP_REWR_CFG, 0x008bb4),
105 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4),
106 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14),
110 REG(ANA_DISCARD_CFG, 0x008c40),
111 REG(ANA_FID_CFG, 0x008c44),
112 REG(ANA_POL_PIR_CFG, 0x004000),
113 REG(ANA_POL_CIR_CFG, 0x004004),
114 REG(ANA_POL_MODE_CFG, 0x004008),
115 REG(ANA_POL_PIR_STATE, 0x00400c),
116 REG(ANA_POL_CIR_STATE, 0x004010),
118 REG(ANA_POL_FLOWC, 0x008c48),
119 REG(ANA_POL_HYST, 0x008cb4),
124 REG(QS_XTR_GRP_CFG, 0x000000),
125 REG(QS_XTR_RD, 0x000008),
126 REG(QS_XTR_FRM_PRUNING, 0x000010),
127 REG(QS_XTR_FLUSH, 0x000018),
128 REG(QS_XTR_DATA_PRESENT, 0x00001c),
129 REG(QS_XTR_CFG, 0x000020),
130 REG(QS_INJ_GRP_CFG, 0x000024),
131 REG(QS_INJ_WR, 0x00002c),
132 REG(QS_INJ_CTRL, 0x000034),
133 REG(QS_INJ_STATUS, 0x00003c),
134 REG(QS_INJ_ERR, 0x000040),
140 REG(VCAP_CORE_UPDATE_CTRL, 0x000000),
141 REG(VCAP_CORE_MV_CFG, 0x000004),
143 REG(VCAP_CACHE_ENTRY_DAT, 0x000008),
144 REG(VCAP_CACHE_MASK_DAT, 0x000108),
145 REG(VCAP_CACHE_ACTION_DAT, 0x000208),
146 REG(VCAP_CACHE_CNT_DAT, 0x000308),
147 REG(VCAP_CACHE_TG_DAT, 0x000388),
149 REG(VCAP_CONST_VCAP_VER, 0x000398),
150 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c),
151 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0),
152 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4),
153 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8),
154 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac),
155 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0),
156 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4),
157 REG(VCAP_CONST_CORE_CNT, 0x0003b8),
158 REG(VCAP_CONST_IF_CNT, 0x0003bc),
162 REG(QSYS_PORT_MODE, 0x00f460),
163 REG(QSYS_SWITCH_PORT_MODE, 0x00f480),
164 REG(QSYS_STAT_CNT_CFG, 0x00f49c),
165 REG(QSYS_EEE_CFG, 0x00f4a0),
166 REG(QSYS_EEE_THRES, 0x00f4b8),
167 REG(QSYS_IGR_NO_SHARING, 0x00f4bc),
168 REG(QSYS_EGR_NO_SHARING, 0x00f4c0),
169 REG(QSYS_SW_STATUS, 0x00f4c4),
170 REG(QSYS_EXT_CPU_CFG, 0x00f4e0),
172 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8),
176 REG(QSYS_TFRM_MISC, 0x00f50c),
177 REG(QSYS_TFRM_PORT_DLY, 0x00f510),
178 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514),
179 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518),
180 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c),
181 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520),
182 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524),
183 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528),
184 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c),
185 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530),
186 REG(QSYS_RED_PROFILE, 0x00f534),
187 REG(QSYS_RES_QOS_MODE, 0x00f574),
188 REG(QSYS_RES_CFG, 0x00c000),
189 REG(QSYS_RES_STAT, 0x00c004),
190 REG(QSYS_EGR_DROP_MODE, 0x00f578),
191 REG(QSYS_EQ_CTRL, 0x00f57c),
193 REG(QSYS_QMAXSDU_CFG_0, 0x00f584),
194 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0),
195 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc),
196 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8),
197 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4),
198 REG(QSYS_QMAXSDU_CFG_5, 0x00f610),
199 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c),
200 REG(QSYS_QMAXSDU_CFG_7, 0x00f648),
201 REG(QSYS_PREEMPTION_CFG, 0x00f664),
202 REG(QSYS_CIR_CFG, 0x000000),
203 REG(QSYS_EIR_CFG, 0x000004),
204 REG(QSYS_SE_CFG, 0x000008),
205 REG(QSYS_SE_DWRR_CFG, 0x00000c),
207 REG(QSYS_SE_DLB_SENSE, 0x000040),
208 REG(QSYS_CIR_STATE, 0x000044),
209 REG(QSYS_EIR_STATE, 0x000048),
211 REG(QSYS_HSCH_MISC_CFG, 0x00f67c),
212 REG(QSYS_TAG_CONFIG, 0x00f680),
213 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698),
214 REG(QSYS_PORT_MAX_SDU, 0x00f69c),
215 REG(QSYS_PARAM_CFG_REG_1, 0x00f440),
216 REG(QSYS_PARAM_CFG_REG_2, 0x00f444),
217 REG(QSYS_PARAM_CFG_REG_3, 0x00f448),
218 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c),
219 REG(QSYS_PARAM_CFG_REG_5, 0x00f450),
220 REG(QSYS_GCL_CFG_REG_1, 0x00f454),
221 REG(QSYS_GCL_CFG_REG_2, 0x00f458),
222 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400),
223 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404),
224 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408),
225 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c),
226 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410),
227 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414),
228 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418),
229 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c),
230 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420),
231 REG(QSYS_GCL_STATUS_REG_1, 0x00f424),
232 REG(QSYS_GCL_STATUS_REG_2, 0x00f428),
236 REG(REW_PORT_VLAN_CFG, 0x000000),
237 REG(REW_TAG_CFG, 0x000004),
238 REG(REW_PORT_CFG, 0x000008),
239 REG(REW_DSCP_CFG, 0x00000c),
240 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
241 REG(REW_PTP_CFG, 0x000050),
242 REG(REW_PTP_DLY1_CFG, 0x000054),
243 REG(REW_RED_TAG_CFG, 0x000058),
244 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410),
245 REG(REW_DSCP_REMAP_CFG, 0x000510),
252 REG(SYS_COUNT_RX_OCTETS, 0x000000),
253 REG(SYS_COUNT_RX_MULTICAST, 0x000008),
254 REG(SYS_COUNT_RX_SHORTS, 0x000010),
255 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
256 REG(SYS_COUNT_RX_JABBERS, 0x000018),
257 REG(SYS_COUNT_RX_64, 0x000024),
258 REG(SYS_COUNT_RX_65_127, 0x000028),
259 REG(SYS_COUNT_RX_128_255, 0x00002c),
260 REG(SYS_COUNT_RX_256_1023, 0x000030),
261 REG(SYS_COUNT_RX_1024_1526, 0x000034),
262 REG(SYS_COUNT_RX_1527_MAX, 0x000038),
263 REG(SYS_COUNT_RX_LONGS, 0x000044),
264 REG(SYS_COUNT_TX_OCTETS, 0x000200),
265 REG(SYS_COUNT_TX_COLLISION, 0x000210),
266 REG(SYS_COUNT_TX_DROPS, 0x000214),
267 REG(SYS_COUNT_TX_64, 0x00021c),
268 REG(SYS_COUNT_TX_65_127, 0x000220),
269 REG(SYS_COUNT_TX_128_511, 0x000224),
270 REG(SYS_COUNT_TX_512_1023, 0x000228),
271 REG(SYS_COUNT_TX_1024_1526, 0x00022c),
272 REG(SYS_COUNT_TX_1527_MAX, 0x000230),
273 REG(SYS_COUNT_TX_AGING, 0x000278),
274 REG(SYS_RESET_CFG, 0x000e00),
275 REG(SYS_SR_ETYPE_CFG, 0x000e04),
276 REG(SYS_VLAN_ETYPE_CFG, 0x000e08),
277 REG(SYS_PORT_MODE, 0x000e0c),
278 REG(SYS_FRONT_PORT_MODE, 0x000e2c),
279 REG(SYS_FRM_AGING, 0x000e44),
280 REG(SYS_STAT_CFG, 0x000e48),
281 REG(SYS_SW_STATUS, 0x000e4c),
283 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c),
284 REG(SYS_REW_MAC_LOW_CFG, 0x000e84),
285 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c),
286 REG(SYS_PAUSE_CFG, 0x000ea0),
287 REG(SYS_PAUSE_TOT_CFG, 0x000ebc),
288 REG(SYS_ATOP, 0x000ec0),
289 REG(SYS_ATOP_TOT_CFG, 0x000edc),
290 REG(SYS_MAC_FC_CFG, 0x000ee0),
291 REG(SYS_MMGT, 0x000ef8),
296 REG(SYS_PTP_STATUS, 0x000f14),
297 REG(SYS_PTP_TXSTAMP, 0x000f18),
298 REG(SYS_PTP_NXT, 0x000f1c),
299 REG(SYS_PTP_CFG, 0x000f20),
300 REG(SYS_RAM_INIT, 0x000f24),
309 REG(PTP_PIN_CFG, 0x000000),
310 REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
311 REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
312 REG(PTP_PIN_TOD_NSEC, 0x00000c),
313 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014),
314 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018),
315 REG(PTP_CFG_MISC, 0x0000a0),
316 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
317 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
321 REG(GCB_SOFT_RST, 0x000004),
325 REG(DEV_CLOCK_CFG, 0x0),
326 REG(DEV_PORT_MISC, 0x4),
327 REG(DEV_EVENTS, 0x8),
328 REG(DEV_EEE_CFG, 0xc),
329 REG(DEV_RX_PATH_DELAY, 0x10),
330 REG(DEV_TX_PATH_DELAY, 0x14),
331 REG(DEV_PTP_PREDICT_CFG, 0x18),
332 REG(DEV_MAC_ENA_CFG, 0x1c),
333 REG(DEV_MAC_MODE_CFG, 0x20),
334 REG(DEV_MAC_MAXLEN_CFG, 0x24),
335 REG(DEV_MAC_TAGS_CFG, 0x28),
336 REG(DEV_MAC_ADV_CHK_CFG, 0x2c),
337 REG(DEV_MAC_IFG_CFG, 0x30),
338 REG(DEV_MAC_HDX_CFG, 0x34),
339 REG(DEV_MAC_DBG_CFG, 0x38),
340 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c),
341 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40),
342 REG(DEV_MAC_STICKY, 0x44),
383 .start = 0x0280000,
384 .end = 0x028ffff,
388 .start = 0x0080000,
389 .end = 0x00800ff,
393 .start = 0x0200000,
394 .end = 0x021ffff,
398 .start = 0x0030000,
399 .end = 0x003ffff,
403 .start = 0x0010000,
404 .end = 0x001ffff,
408 .start = 0x0040000,
409 .end = 0x00403ff,
413 .start = 0x0050000,
414 .end = 0x00503ff,
418 .start = 0x0060000,
419 .end = 0x00603ff,
423 .start = 0x0090000,
424 .end = 0x00900cb,
428 .start = 0x0070000,
429 .end = 0x00701ff,
436 .start = 0x0100000,
437 .end = 0x010ffff,
441 .start = 0x0110000,
442 .end = 0x011ffff,
446 .start = 0x0120000,
447 .end = 0x012ffff,
451 .start = 0x0130000,
452 .end = 0x013ffff,
456 .start = 0x0140000,
457 .end = 0x014ffff,
461 .start = 0x0150000,
462 .end = 0x015ffff,
467 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
471 .start = 0x8030,
472 .end = 0x8040,
478 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
504 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
507 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
508 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
509 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
516 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
520 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
523 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
527 { .offset = 0x00, .name = "rx_octets", },
528 { .offset = 0x01, .name = "rx_unicast", },
529 { .offset = 0x02, .name = "rx_multicast", },
530 { .offset = 0x03, .name = "rx_broadcast", },
531 { .offset = 0x04, .name = "rx_shorts", },
532 { .offset = 0x05, .name = "rx_fragments", },
533 { .offset = 0x06, .name = "rx_jabbers", },
534 { .offset = 0x07, .name = "rx_crc_align_errs", },
535 { .offset = 0x08, .name = "rx_sym_errs", },
536 { .offset = 0x09, .name = "rx_frames_below_65_octets", },
537 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", },
538 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", },
539 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", },
540 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", },
541 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", },
542 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", },
543 { .offset = 0x10, .name = "rx_pause", },
544 { .offset = 0x11, .name = "rx_control", },
545 { .offset = 0x12, .name = "rx_longs", },
546 { .offset = 0x13, .name = "rx_classified_drops", },
547 { .offset = 0x14, .name = "rx_red_prio_0", },
548 { .offset = 0x15, .name = "rx_red_prio_1", },
549 { .offset = 0x16, .name = "rx_red_prio_2", },
550 { .offset = 0x17, .name = "rx_red_prio_3", },
551 { .offset = 0x18, .name = "rx_red_prio_4", },
552 { .offset = 0x19, .name = "rx_red_prio_5", },
553 { .offset = 0x1A, .name = "rx_red_prio_6", },
554 { .offset = 0x1B, .name = "rx_red_prio_7", },
555 { .offset = 0x1C, .name = "rx_yellow_prio_0", },
556 { .offset = 0x1D, .name = "rx_yellow_prio_1", },
557 { .offset = 0x1E, .name = "rx_yellow_prio_2", },
558 { .offset = 0x1F, .name = "rx_yellow_prio_3", },
559 { .offset = 0x20, .name = "rx_yellow_prio_4", },
560 { .offset = 0x21, .name = "rx_yellow_prio_5", },
561 { .offset = 0x22, .name = "rx_yellow_prio_6", },
562 { .offset = 0x23, .name = "rx_yellow_prio_7", },
563 { .offset = 0x24, .name = "rx_green_prio_0", },
564 { .offset = 0x25, .name = "rx_green_prio_1", },
565 { .offset = 0x26, .name = "rx_green_prio_2", },
566 { .offset = 0x27, .name = "rx_green_prio_3", },
567 { .offset = 0x28, .name = "rx_green_prio_4", },
568 { .offset = 0x29, .name = "rx_green_prio_5", },
569 { .offset = 0x2A, .name = "rx_green_prio_6", },
570 { .offset = 0x2B, .name = "rx_green_prio_7", },
571 { .offset = 0x80, .name = "tx_octets", },
572 { .offset = 0x81, .name = "tx_unicast", },
573 { .offset = 0x82, .name = "tx_multicast", },
574 { .offset = 0x83, .name = "tx_broadcast", },
575 { .offset = 0x84, .name = "tx_collision", },
576 { .offset = 0x85, .name = "tx_drops", },
577 { .offset = 0x86, .name = "tx_pause", },
578 { .offset = 0x87, .name = "tx_frames_below_65_octets", },
579 { .offset = 0x88, .name = "tx_frames_65_to_127_octets", },
580 { .offset = 0x89, .name = "tx_frames_128_255_octets", },
581 { .offset = 0x8A, .name = "tx_frames_256_511_octets", },
582 { .offset = 0x8B, .name = "tx_frames_512_1023_octets", },
583 { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", },
584 { .offset = 0x8D, .name = "tx_frames_over_1526_octets", },
585 { .offset = 0x8E, .name = "tx_yellow_prio_0", },
586 { .offset = 0x8F, .name = "tx_yellow_prio_1", },
587 { .offset = 0x90, .name = "tx_yellow_prio_2", },
588 { .offset = 0x91, .name = "tx_yellow_prio_3", },
589 { .offset = 0x92, .name = "tx_yellow_prio_4", },
590 { .offset = 0x93, .name = "tx_yellow_prio_5", },
591 { .offset = 0x94, .name = "tx_yellow_prio_6", },
592 { .offset = 0x95, .name = "tx_yellow_prio_7", },
593 { .offset = 0x96, .name = "tx_green_prio_0", },
594 { .offset = 0x97, .name = "tx_green_prio_1", },
595 { .offset = 0x98, .name = "tx_green_prio_2", },
596 { .offset = 0x99, .name = "tx_green_prio_3", },
597 { .offset = 0x9A, .name = "tx_green_prio_4", },
598 { .offset = 0x9B, .name = "tx_green_prio_5", },
599 { .offset = 0x9C, .name = "tx_green_prio_6", },
600 { .offset = 0x9D, .name = "tx_green_prio_7", },
601 { .offset = 0x9E, .name = "tx_aged", },
602 { .offset = 0x100, .name = "drop_local", },
603 { .offset = 0x101, .name = "drop_tail", },
604 { .offset = 0x102, .name = "drop_yellow_prio_0", },
605 { .offset = 0x103, .name = "drop_yellow_prio_1", },
606 { .offset = 0x104, .name = "drop_yellow_prio_2", },
607 { .offset = 0x105, .name = "drop_yellow_prio_3", },
608 { .offset = 0x106, .name = "drop_yellow_prio_4", },
609 { .offset = 0x107, .name = "drop_yellow_prio_5", },
610 { .offset = 0x108, .name = "drop_yellow_prio_6", },
611 { .offset = 0x109, .name = "drop_yellow_prio_7", },
612 { .offset = 0x10A, .name = "drop_green_prio_0", },
613 { .offset = 0x10B, .name = "drop_green_prio_1", },
614 { .offset = 0x10C, .name = "drop_green_prio_2", },
615 { .offset = 0x10D, .name = "drop_green_prio_3", },
616 { .offset = 0x10E, .name = "drop_green_prio_4", },
617 { .offset = 0x10F, .name = "drop_green_prio_5", },
618 { .offset = 0x110, .name = "drop_green_prio_6", },
619 { .offset = 0x111, .name = "drop_green_prio_7", },
623 [VCAP_ES0_EGR_PORT] = { 0, 3},
634 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2},
655 [VCAP_IS1_HK_TYPE] = { 0, 1},
706 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1},
731 [VCAP_IS2_TYPE] = { 0, 4},
810 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1},
829 .action_type_width = 0,
841 .action_type_width = 0,
873 .max_adj = 0x7fffffff,
874 .n_alarm = 0,
875 .n_ext_ts = 0,
878 .pps = 0,
935 return 0; in vsc9959_reset()
943 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; in vsc9959_phylink_validate()
982 return 0; in vsc9959_prevalidate_phy_mode()
990 return 0; in vsc9959_prevalidate_phy_mode()
997 * Bit 8: Unit; 0:1, 1:16
998 * Bit 7-0: Value to be multiplied with unit
1067 mdio_priv->mdio_base = 0; in vsc9959_mdio_bus_alloc()
1072 if (rc < 0) { in vsc9959_mdio_bus_alloc()
1079 for (port = 0; port < felix->info->num_ports; port++) { in vsc9959_mdio_bus_alloc()
1105 return 0; in vsc9959_mdio_bus_alloc()
1113 for (port = 0; port < ocelot->num_phys_ports; port++) { in vsc9959_mdio_bus_free()
1200 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF), in vsc9959_qos_port_tas_set()
1205 return 0; in vsc9959_qos_port_tas_set()
1230 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | in vsc9959_qos_port_tas_set()
1231 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), in vsc9959_qos_port_tas_set()
1249 for (i = 0; i < taprio->num_entries; i++) in vsc9959_qos_port_tas_set()
1274 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | in vsc9959_qos_port_cbs_set()
1275 QSYS_CIR_CFG_CIR_BURST(0), in vsc9959_qos_port_cbs_set()
1278 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, in vsc9959_qos_port_cbs_set()
1281 return 0; in vsc9959_qos_port_cbs_set()
1287 rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); in vsc9959_qos_port_cbs_set()
1291 burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); in vsc9959_qos_port_cbs_set()
1299 QSYS_SE_CFG_SE_FRM_MODE(0) | in vsc9959_qos_port_cbs_set()
1306 return 0; in vsc9959_qos_port_cbs_set()
1343 packing(injection, &bypass, 127, 127, OCELOT_TAG_LEN, PACK, 0); in vsc9959_xmit_template_populate()
1344 packing(injection, &dest, 68, 56, OCELOT_TAG_LEN, PACK, 0); in vsc9959_xmit_template_populate()
1345 packing(injection, &src, 46, 43, OCELOT_TAG_LEN, PACK, 0); in vsc9959_xmit_template_populate()
1347 *prefix = cpu_to_be32(0x8880000a); in vsc9959_xmit_template_populate()
1365 .imdio_pci_bar = 0,
1418 "DMA configuration failed: 0x%x\n", err); in felix_pci_probe()
1472 return 0; in felix_pci_probe()
1503 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
1505 { 0, }