Lines Matching +full:0 +full:x610
18 #define PHY_ID_QCA8337 0x004dd036
19 #define QCA8K_ID_QCA8337 0x13
23 #define QCA8K_CPU_PORT 0
28 #define QCA8K_REG_MASK_CTRL 0x000
29 #define QCA8K_MASK_CTRL_ID_M 0xff
31 #define QCA8K_REG_PORT0_PAD_CTRL 0x004
32 #define QCA8K_REG_PORT5_PAD_CTRL 0x008
33 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c
36 ((0x8 + (x & 0x3)) << 22)
38 ((0x10 + (x & 0x3)) << 20)
42 #define QCA8K_REG_PWS 0x010
44 #define QCA8K_REG_MODULE_EN 0x030
45 #define QCA8K_MODULE_EN_MIB BIT(0)
46 #define QCA8K_REG_MIB 0x034
50 #define QCA8K_MDIO_MASTER_CTRL 0x3c
54 #define QCA8K_MDIO_MASTER_WRITE 0
59 #define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
62 #define QCA8K_GOL_MAC_ADDR0 0x60
63 #define QCA8K_GOL_MAC_ADDR1 0x64
64 #define QCA8K_MAX_FRAME_SIZE 0x78
65 #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
66 #define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
67 #define QCA8K_PORT_STATUS_SPEED_10 0
68 #define QCA8K_PORT_STATUS_SPEED_100 0x1
69 #define QCA8K_PORT_STATUS_SPEED_1000 0x2
79 #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
82 #define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
83 #define QCA8K_PORT_HDR_CTRL_TX_S 0
86 #define QCA8K_PORT_HDR_CTRL_NONE 0
87 #define QCA8K_REG_SGMII_CTRL 0x0e0
94 #define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
99 #define QCA8K_REG_EEE_CTRL 0x100
103 #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
106 #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
107 #define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
108 #define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
111 #define QCA8K_REG_ATU_DATA0 0x600
115 #define QCA8K_REG_ATU_DATA1 0x604
116 #define QCA8K_ATU_PORT_M 0x7f
119 #define QCA8K_REG_ATU_DATA2 0x608
120 #define QCA8K_ATU_VID_M 0xfff
122 #define QCA8K_ATU_STATUS_M 0xf
123 #define QCA8K_ATU_STATUS_STATIC 0xf
124 #define QCA8K_REG_ATU_FUNC 0x60c
129 #define QCA8K_ATU_FUNC_PORT_M 0xf
131 #define QCA8K_REG_VTU_FUNC0 0x610
136 #define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
140 #define QCA8K_REG_VTU_FUNC1 0x614
144 #define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
146 #define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
150 #define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
151 #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
152 #define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
154 #define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
159 #define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
168 #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
171 #define QCA8K_HROUTER_CONTROL 0xe00
175 #define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
176 #define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
177 #define QCA8K_HNAT_CONTROL 0xe38
180 #define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
183 #define MII_ATH_MMD_ADDR 0x0d
184 #define MII_ATH_MMD_DATA 0x0e
187 QCA8K_PORT_SPEED_10M = 0,