Lines Matching +full:0 +full:x00a10000
70 #define PRPH_BASE (0x00000)
71 #define PRPH_END (0xFFFFF)
74 #define APMG_BASE (PRPH_BASE + 0x3000)
75 #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
76 #define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
77 #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
78 #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
79 #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
80 #define APMG_RFKILL_REG (APMG_BASE + 0x0014)
81 #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
82 #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
83 #define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)
84 #define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)
86 #define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
87 #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
88 #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
90 #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
91 #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
92 #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
93 #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
94 #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
95 #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
96 #define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
98 #define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200)
99 #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
100 #define APMG_PCIDEV_STT_VAL_WAKE_ME (0x00004000)
102 #define APMG_RTC_INT_STT_RFKILL (0x10000000)
105 #define DEVICE_SYSTEM_TIME_REG 0xA0206C
108 #define DEVICE_SET_NMI_REG 0x00a01c30
111 #define UREG_NIC_SET_NMI_DRIVER 0x00a05c10
112 #define UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER_MSK 0xff000000
114 /* Shared registers (0x0..0x3ff, via target indirect or periphery */
115 #define SHR_BASE 0x00a10000
118 #define SHR_APMG_GP1_REG 0x01dc
120 #define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004
121 #define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000
124 #define SHR_APMG_DL_CFG_REG 0x01c4
126 #define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0
127 #define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080
128 #define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100
131 #define SHR_APMG_XTAL_CFG_REG 0x1c0
132 #define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000
138 #define RELEASE_CPU_RESET (0x300C)
145 #define SHR_MISC_WFM_DTS_EN (0x00a10024)
146 #define DTSC_CFG_MODE (0x00a10604)
147 #define DTSC_VREF_AVG (0x00a10648)
148 #define DTSC_VREF5_AVG (0x00a1064c)
149 #define DTSC_CFG_MODE_PERIODIC (0x2)
150 #define DTSC_PTAT_AVG (0x00a10650)
168 * 0 -- EDCA BK (background) frames, lowest priority
177 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
179 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
224 #define SCD_MEM_LOWER_BOUND (0x0000)
234 #define SCD_TXFIFO_POS_TID (0)
236 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
239 #define SCD_QUEUE_STTS_REG_POS_TXF (0)
243 #define SCD_QUEUE_STTS_REG_MSK (0x017F0000)
245 #define SCD_QUEUE_CTX_REG1_CREDIT (0x00FFFF00)
246 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT (0xFF000000)
249 #define SCD_QUEUE_CTX_REG2_WIN_SIZE (0x0000007F)
250 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT (0x007F0000)
253 #define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0)
257 #define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)
258 #define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
261 #define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
262 #define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
265 #define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
266 #define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808)
275 ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
277 #define SCD_BASE (PRPH_BASE + 0xa02c00)
279 #define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0)
280 #define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8)
281 #define SCD_AIT (SCD_BASE + 0x0c)
282 #define SCD_TXFACT (SCD_BASE + 0x10)
283 #define SCD_ACTIVE (SCD_BASE + 0x14)
284 #define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8)
285 #define SCD_CHAINEXT_EN (SCD_BASE + 0x244)
286 #define SCD_AGGR_SEL (SCD_BASE + 0x248)
287 #define SCD_INTERRUPT_MASK (SCD_BASE + 0x108)
288 #define SCD_GP_CTRL (SCD_BASE + 0x1a8)
289 #define SCD_EN_CTRL (SCD_BASE + 0x254)
294 #define OSC_CLK (0xa04068)
295 #define OSC_CLK_FORCE_CONTROL (0x8)
297 #define FH_UCODE_LOAD_STATUS (0x1AF0)
304 #define UREG_UCODE_LOAD_STATUS (0xa05c40)
305 #define UREG_CPU_INIT_RUN (0xa05c44)
307 #define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78)
308 #define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C)
310 #define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000)
311 #define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400)
313 #define LMAC2_PRPH_OFFSET (0x100000)
316 #define RXF_SIZE_ADDR (0xa00c88)
317 #define RXF_RD_D_SPACE (0xa00c40)
318 #define RXF_RD_WR_PTR (0xa00c50)
319 #define RXF_RD_RD_PTR (0xa00c54)
320 #define RXF_RD_FENCE_PTR (0xa00c4c)
321 #define RXF_SET_FENCE_MODE (0xa00c14)
322 #define RXF_LD_WR2FENCE (0xa00c1c)
323 #define RXF_FIFO_RD_FENCE_INC (0xa00c68)
325 #define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS)
326 #define RXF_DIFF_FROM_PREV (0x200)
327 #define RXF2C_DIFF_FROM_PREV (0x4e00)
329 #define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10)
330 #define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c)
333 #define TXF_FIFO_ITEM_CNT (0xa00438)
334 #define TXF_WR_PTR (0xa00414)
335 #define TXF_RD_PTR (0xa00410)
336 #define TXF_FENCE_PTR (0xa00418)
337 #define TXF_LOCK_FENCE (0xa00424)
338 #define TXF_LARC_NUM (0xa0043c)
339 #define TXF_READ_MODIFY_DATA (0xa00448)
340 #define TXF_READ_MODIFY_ADDR (0xa0044c)
343 #define TXF_CPU2_FIFO_ITEM_CNT (0xA00538)
344 #define TXF_CPU2_WR_PTR (0xA00514)
345 #define TXF_CPU2_RD_PTR (0xA00510)
346 #define TXF_CPU2_FENCE_PTR (0xA00518)
347 #define TXF_CPU2_LOCK_FENCE (0xA00524)
348 #define TXF_CPU2_NUM (0xA0053C)
349 #define TXF_CPU2_READ_MODIFY_DATA (0xA00548)
350 #define TXF_CPU2_READ_MODIFY_ADDR (0xA0054C)
353 #define RSP_RADIO_CMD (0xa02804)
354 #define RSP_RADIO_RDDAT (0xa02814)
359 #define HPM_MAC_LTR_CSR 0xa0348c
360 #define HPM_MAC_LRT_ENABLE_ALL 0xf
362 #define HPM_UMAC_LTR 0xa03480
365 #define MON_BUFF_SAMPLE_CTL (0xa03c00)
366 #define MON_BUFF_BASE_ADDR (0xa03c1c)
367 #define MON_BUFF_END_ADDR (0xa03c40)
368 #define MON_BUFF_WRPTR (0xa03c44)
369 #define MON_BUFF_CYCLE_CNT (0xa03c48)
371 #define MON_BUFF_BASE_ADDR_VER2 (0xa03c1c)
372 #define MON_BUFF_END_ADDR_VER2 (0xa03c20)
373 #define MON_BUFF_WRPTR_VER2 (0xa03c24)
374 #define MON_BUFF_CYCLE_CNT_VER2 (0xa03c28)
375 #define MON_BUFF_SHIFT_VER2 (0x8)
377 #define DBGC_CUR_DBGBUF_BASE_ADDR_LSB (0xd03c20)
378 #define DBGC_CUR_DBGBUF_BASE_ADDR_MSB (0xd03c24)
379 #define DBGC_CUR_DBGBUF_STATUS (0xd03c1c)
380 #define DBGC_DBGBUF_WRAP_AROUND (0xd03c2c)
381 #define DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK (0x00ffffff)
382 #define DBGC_CUR_DBGBUF_STATUS_IDX_MSK (0x0f000000)
384 #define MON_DMARB_RD_CTL_ADDR (0xa03c60)
385 #define MON_DMARB_RD_DATA_ADDR (0xa03c5c)
387 #define DBGC_IN_SAMPLE (0xa03c00)
388 #define DBGC_OUT_CTRL (0xa03c0c)
391 #define LDBG_M2S_BUF_WPTR (0xa0476c)
392 #define LDBG_M2S_BUF_WRAP_CNT (0xa04774)
393 #define LDBG_M2S_BUF_WPTR_VAL_MSK (0x000fffff)
394 #define LDBG_M2S_BUF_WRAP_CNT_VAL_MSK (0x000fffff)
397 #define WFPM_PS_CTL_CLR 0xA0300C
398 #define WFMP_MAC_ADDR_0 0xA03080
399 #define WFMP_MAC_ADDR_1 0xA03084
400 #define LMPM_PMG_EN 0xA01CEC
401 #define RADIO_REG_SYS_MANUAL_DFT_0 0xAD4078
402 #define RFIC_REG_RD 0xAD0470
403 #define WFPM_CTRL_REG 0xA03030
404 #define WFPM_GP2 0xA030B4
407 WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000,
410 #define CNVI_AUX_MISC_CHIP 0xA200B0
411 #define CNVR_AUX_MISC_CHIP 0xA2B800
412 #define CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM 0xA29890
413 #define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR 0xA29938
419 #define PREG_AUX_BUS_WPROT_0 0xA04CC0
422 #define PREG_PRPH_WPROT_9000 0xA04CE0
424 #define PREG_PRPH_WPROT_22000 0xA04D00
426 #define SB_CPU_1_STATUS 0xA01E30
427 #define SB_CPU_2_STATUS 0xA01E34
428 #define UMAG_SB_CPU_1_STATUS 0xA038C0
429 #define UMAG_SB_CPU_2_STATUS 0xA038C4
430 #define UMAG_GEN_HW_STATUS 0xA038C8
431 #define UREG_UMAC_CURRENT_PC 0xa05c18
432 #define UREG_LMAC1_CURRENT_PC 0xa05c1c
433 #define UREG_LMAC2_CURRENT_PC 0xa05c20
441 #define LMPM_CHICK 0xA01FF8
443 LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0),
447 #define LMPM_PAGE_PASS_NOTIF 0xA03824
452 #define UREG_CHICK (0xA05C00)
456 #define HPM_DEBUG 0xA03440
460 #define HPM_HIPM_GEN_CFG 0xA03458
461 #define HPM_HIPM_GEN_CFG_CR_PG_EN BIT(0)
465 #define UREG_DOORBELL_TO_ISR6 0xA05C04
466 #define UREG_DOORBELL_TO_ISR6_NMI_BIT BIT(0)
471 #define FSEQ_ERROR_CODE 0xA340C8
472 #define FSEQ_TOP_INIT_VERSION 0xA34038
473 #define FSEQ_CNVIO_INIT_VERSION 0xA3403C
474 #define FSEQ_OTP_VERSION 0xA340FC
475 #define FSEQ_TOP_CONTENT_VERSION 0xA340F4
476 #define FSEQ_ALIVE_TOKEN 0xA340F0
477 #define FSEQ_CNVI_ID 0xA3408C
478 #define FSEQ_CNVR_ID 0xA34090
480 #define IWL_D3_SLEEP_STATUS_SUSPEND 0xD3
481 #define IWL_D3_SLEEP_STATUS_RESUME 0xD0