6  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
93 		: "r" (reset->ramc_base[0]),  in at91_reset()
94 		  "r" (reset->ramc_base[1]),  in at91_reset()
95 		  "r" (reset->rstc_base),  in at91_reset()
98 		  "r" (reset->args),  in at91_reset()
99 		  "r" (reset->ramc_lpr)  in at91_reset()
141 	dev_info(&pdev->dev, "Starting after %s\n", reason);  in at91_reset_status()
146 		.compatible = "atmel,at91sam9260-sdramc",
150 		.compatible = "atmel,at91sam9g45-ddramc",
158 		.compatible = "atmel,at91sam9260-rstc",
163 		.compatible = "atmel,at91sam9g45-rstc",
168 		.compatible = "atmel,sama5d3-rstc",
173 		.compatible = "atmel,samx7-rstc",
177 		.compatible = "microchip,sam9x60-rstc",
191 	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);  in at91_reset_probe()
193 		return -ENOMEM;  in at91_reset_probe()
195 	reset->rstc_base = of_iomap(pdev->dev.of_node, 0);  in at91_reset_probe()
196 	if (!reset->rstc_base) {  in at91_reset_probe()
197 		dev_err(&pdev->dev, "Could not map reset controller address\n");  in at91_reset_probe()
198 		return -ENODEV;  in at91_reset_probe()
201 	if (!of_device_is_compatible(pdev->dev.of_node, "atmel,sama5d3-rstc")) {  in at91_reset_probe()
204 			reset->ramc_lpr = (u32)match->data;  in at91_reset_probe()
205 			reset->ramc_base[idx] = of_iomap(np, 0);  in at91_reset_probe()
206 			if (!reset->ramc_base[idx]) {  in at91_reset_probe()
207 				dev_err(&pdev->dev, "Could not map ram controller address\n");  in at91_reset_probe()
209 				return -ENODEV;  in at91_reset_probe()
215 	match = of_match_node(at91_reset_of_match, pdev->dev.of_node);  in at91_reset_probe()
216 	reset->nb.notifier_call = at91_reset;  in at91_reset_probe()
217 	reset->nb.priority = 192;  in at91_reset_probe()
218 	reset->args = (u32)match->data;  in at91_reset_probe()
220 	reset->sclk = devm_clk_get(&pdev->dev, NULL);  in at91_reset_probe()
221 	if (IS_ERR(reset->sclk))  in at91_reset_probe()
222 		return PTR_ERR(reset->sclk);  in at91_reset_probe()
224 	ret = clk_prepare_enable(reset->sclk);  in at91_reset_probe()
226 		dev_err(&pdev->dev, "Could not enable slow clock\n");  in at91_reset_probe()
232 	if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) {  in at91_reset_probe()
233 		u32 val = readl(reset->rstc_base + AT91_RSTC_MR);  in at91_reset_probe()
236 		       reset->rstc_base + AT91_RSTC_MR);  in at91_reset_probe()
239 	ret = register_restart_handler(&reset->nb);  in at91_reset_probe()
241 		clk_disable_unprepare(reset->sclk);  in at91_reset_probe()
245 	at91_reset_status(pdev, reset->rstc_base);  in at91_reset_probe()
254 	unregister_restart_handler(&reset->nb);  in at91_reset_remove()
255 	clk_disable_unprepare(reset->sclk);  in at91_reset_remove()
263 		.name = "at91-reset",