Lines Matching +full:tegra20 +full:- +full:slink
1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
12 #include <linux/dma-mapping.h>
213 return readl(tspi->base + reg); in tegra_slink_readl()
219 writel(val, tspi->base + reg); in tegra_slink_writel()
223 readl(tspi->base + SLINK_MAS_DATA); in tegra_slink_writel()
240 switch (tspi->bytes_per_word) { in tegra_slink_get_packed_size()
258 unsigned remain_len = t->len - tspi->cur_pos; in tegra_slink_calculate_curr_xfer_param()
264 bits_per_word = t->bits_per_word; in tegra_slink_calculate_curr_xfer_param()
265 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_slink_calculate_curr_xfer_param()
268 tspi->is_packed = true; in tegra_slink_calculate_curr_xfer_param()
269 tspi->words_per_32bit = 32/bits_per_word; in tegra_slink_calculate_curr_xfer_param()
271 tspi->is_packed = false; in tegra_slink_calculate_curr_xfer_param()
272 tspi->words_per_32bit = 1; in tegra_slink_calculate_curr_xfer_param()
274 tspi->packed_size = tegra_slink_get_packed_size(tspi, t); in tegra_slink_calculate_curr_xfer_param()
276 if (tspi->is_packed) { in tegra_slink_calculate_curr_xfer_param()
277 max_len = min(remain_len, tspi->max_buf_size); in tegra_slink_calculate_curr_xfer_param()
278 tspi->curr_dma_words = max_len/tspi->bytes_per_word; in tegra_slink_calculate_curr_xfer_param()
281 max_word = (remain_len - 1) / tspi->bytes_per_word + 1; in tegra_slink_calculate_curr_xfer_param()
282 max_word = min(max_word, tspi->max_buf_size/4); in tegra_slink_calculate_curr_xfer_param()
283 tspi->curr_dma_words = max_word; in tegra_slink_calculate_curr_xfer_param()
299 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_slink_fill_tx_fifo_from_client_txbuf()
304 if (tspi->is_packed) { in tegra_slink_fill_tx_fifo_from_client_txbuf()
305 fifo_words_left = tx_empty_count * tspi->words_per_32bit; in tegra_slink_fill_tx_fifo_from_client_txbuf()
306 written_words = min(fifo_words_left, tspi->curr_dma_words); in tegra_slink_fill_tx_fifo_from_client_txbuf()
307 nbytes = written_words * tspi->bytes_per_word; in tegra_slink_fill_tx_fifo_from_client_txbuf()
311 for (i = 0; (i < 4) && nbytes; i++, nbytes--) in tegra_slink_fill_tx_fifo_from_client_txbuf()
316 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); in tegra_slink_fill_tx_fifo_from_client_txbuf()
318 nbytes = written_words * tspi->bytes_per_word; in tegra_slink_fill_tx_fifo_from_client_txbuf()
321 for (i = 0; nbytes && (i < tspi->bytes_per_word); in tegra_slink_fill_tx_fifo_from_client_txbuf()
322 i++, nbytes--) in tegra_slink_fill_tx_fifo_from_client_txbuf()
327 tspi->cur_tx_pos += written_words * tspi->bytes_per_word; in tegra_slink_fill_tx_fifo_from_client_txbuf()
339 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; in tegra_slink_read_rx_fifo_to_client_rxbuf()
343 if (tspi->is_packed) { in tegra_slink_read_rx_fifo_to_client_rxbuf()
344 len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_read_rx_fifo_to_client_rxbuf()
347 for (i = 0; len && (i < 4); i++, len--) in tegra_slink_read_rx_fifo_to_client_rxbuf()
350 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_read_rx_fifo_to_client_rxbuf()
351 read_words += tspi->curr_dma_words; in tegra_slink_read_rx_fifo_to_client_rxbuf()
355 for (i = 0; (i < tspi->bytes_per_word); i++) in tegra_slink_read_rx_fifo_to_client_rxbuf()
358 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; in tegra_slink_read_rx_fifo_to_client_rxbuf()
368 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, in tegra_slink_copy_client_txbuf_to_spi_txbuf()
369 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_slink_copy_client_txbuf_to_spi_txbuf()
371 if (tspi->is_packed) { in tegra_slink_copy_client_txbuf_to_spi_txbuf()
372 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_copy_client_txbuf_to_spi_txbuf()
373 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); in tegra_slink_copy_client_txbuf_to_spi_txbuf()
377 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_slink_copy_client_txbuf_to_spi_txbuf()
378 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_copy_client_txbuf_to_spi_txbuf()
380 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_slink_copy_client_txbuf_to_spi_txbuf()
382 for (i = 0; consume && (i < tspi->bytes_per_word); in tegra_slink_copy_client_txbuf_to_spi_txbuf()
383 i++, consume--) in tegra_slink_copy_client_txbuf_to_spi_txbuf()
385 tspi->tx_dma_buf[count] = x; in tegra_slink_copy_client_txbuf_to_spi_txbuf()
388 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_copy_client_txbuf_to_spi_txbuf()
391 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, in tegra_slink_copy_client_txbuf_to_spi_txbuf()
392 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_slink_copy_client_txbuf_to_spi_txbuf()
401 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
402 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
404 if (tspi->is_packed) { in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
405 len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
406 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
410 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
411 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
413 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
414 u32 x = tspi->rx_dma_buf[count] & rx_mask; in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
415 for (i = 0; (i < tspi->bytes_per_word); i++) in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
419 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
422 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
423 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
435 reinit_completion(&tspi->tx_dma_complete); in tegra_slink_start_tx_dma()
436 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, in tegra_slink_start_tx_dma()
437 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, in tegra_slink_start_tx_dma()
439 if (!tspi->tx_dma_desc) { in tegra_slink_start_tx_dma()
440 dev_err(tspi->dev, "Not able to get desc for Tx\n"); in tegra_slink_start_tx_dma()
441 return -EIO; in tegra_slink_start_tx_dma()
444 tspi->tx_dma_desc->callback = tegra_slink_dma_complete; in tegra_slink_start_tx_dma()
445 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; in tegra_slink_start_tx_dma()
447 dmaengine_submit(tspi->tx_dma_desc); in tegra_slink_start_tx_dma()
448 dma_async_issue_pending(tspi->tx_dma_chan); in tegra_slink_start_tx_dma()
454 reinit_completion(&tspi->rx_dma_complete); in tegra_slink_start_rx_dma()
455 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, in tegra_slink_start_rx_dma()
456 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, in tegra_slink_start_rx_dma()
458 if (!tspi->rx_dma_desc) { in tegra_slink_start_rx_dma()
459 dev_err(tspi->dev, "Not able to get desc for Rx\n"); in tegra_slink_start_rx_dma()
460 return -EIO; in tegra_slink_start_rx_dma()
463 tspi->rx_dma_desc->callback = tegra_slink_dma_complete; in tegra_slink_start_rx_dma()
464 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; in tegra_slink_start_rx_dma()
466 dmaengine_submit(tspi->rx_dma_desc); in tegra_slink_start_rx_dma()
467 dma_async_issue_pending(tspi->rx_dma_chan); in tegra_slink_start_rx_dma()
482 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n", in tegra_slink_start_dma_based_transfer()
484 return -EIO; in tegra_slink_start_dma_based_transfer()
487 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1); in tegra_slink_start_dma_based_transfer()
488 val |= tspi->packed_size; in tegra_slink_start_dma_based_transfer()
489 if (tspi->is_packed) in tegra_slink_start_dma_based_transfer()
490 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, in tegra_slink_start_dma_based_transfer()
493 len = tspi->curr_dma_words * 4; in tegra_slink_start_dma_based_transfer()
503 if (tspi->cur_direction & DATA_DIR_TX) in tegra_slink_start_dma_based_transfer()
506 if (tspi->cur_direction & DATA_DIR_RX) in tegra_slink_start_dma_based_transfer()
510 tspi->dma_control_reg = val; in tegra_slink_start_dma_based_transfer()
512 if (tspi->cur_direction & DATA_DIR_TX) { in tegra_slink_start_dma_based_transfer()
517 dev_err(tspi->dev, in tegra_slink_start_dma_based_transfer()
522 /* Wait for tx fifo to be fill before starting slink */ in tegra_slink_start_dma_based_transfer()
528 if (tspi->cur_direction & DATA_DIR_RX) { in tegra_slink_start_dma_based_transfer()
530 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_slink_start_dma_based_transfer()
531 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_slink_start_dma_based_transfer()
535 dev_err(tspi->dev, in tegra_slink_start_dma_based_transfer()
537 if (tspi->cur_direction & DATA_DIR_TX) in tegra_slink_start_dma_based_transfer()
538 dmaengine_terminate_all(tspi->tx_dma_chan); in tegra_slink_start_dma_based_transfer()
542 tspi->is_curr_dma_xfer = true; in tegra_slink_start_dma_based_transfer()
543 if (tspi->is_packed) { in tegra_slink_start_dma_based_transfer()
549 tspi->dma_control_reg = val; in tegra_slink_start_dma_based_transfer()
562 val = tspi->packed_size; in tegra_slink_start_cpu_based_transfer()
563 if (tspi->cur_direction & DATA_DIR_TX) in tegra_slink_start_cpu_based_transfer()
566 if (tspi->cur_direction & DATA_DIR_RX) in tegra_slink_start_cpu_based_transfer()
570 tspi->dma_control_reg = val; in tegra_slink_start_cpu_based_transfer()
572 if (tspi->cur_direction & DATA_DIR_TX) in tegra_slink_start_cpu_based_transfer()
575 cur_words = tspi->curr_dma_words; in tegra_slink_start_cpu_based_transfer()
576 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1); in tegra_slink_start_cpu_based_transfer()
578 tspi->dma_control_reg = val; in tegra_slink_start_cpu_based_transfer()
580 tspi->is_curr_dma_xfer = false; in tegra_slink_start_cpu_based_transfer()
581 if (tspi->is_packed) { in tegra_slink_start_cpu_based_transfer()
587 tspi->dma_control_reg = val; in tegra_slink_start_cpu_based_transfer()
602 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); in tegra_slink_init_dma_param()
604 return dev_err_probe(tspi->dev, PTR_ERR(dma_chan), in tegra_slink_init_dma_param()
607 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, in tegra_slink_init_dma_param()
610 dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); in tegra_slink_init_dma_param()
612 return -ENOMEM; in tegra_slink_init_dma_param()
616 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; in tegra_slink_init_dma_param()
620 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO; in tegra_slink_init_dma_param()
629 tspi->rx_dma_chan = dma_chan; in tegra_slink_init_dma_param()
630 tspi->rx_dma_buf = dma_buf; in tegra_slink_init_dma_param()
631 tspi->rx_dma_phys = dma_phys; in tegra_slink_init_dma_param()
633 tspi->tx_dma_chan = dma_chan; in tegra_slink_init_dma_param()
634 tspi->tx_dma_buf = dma_buf; in tegra_slink_init_dma_param()
635 tspi->tx_dma_phys = dma_phys; in tegra_slink_init_dma_param()
640 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); in tegra_slink_init_dma_param()
653 dma_buf = tspi->rx_dma_buf; in tegra_slink_deinit_dma_param()
654 dma_chan = tspi->rx_dma_chan; in tegra_slink_deinit_dma_param()
655 dma_phys = tspi->rx_dma_phys; in tegra_slink_deinit_dma_param()
656 tspi->rx_dma_chan = NULL; in tegra_slink_deinit_dma_param()
657 tspi->rx_dma_buf = NULL; in tegra_slink_deinit_dma_param()
659 dma_buf = tspi->tx_dma_buf; in tegra_slink_deinit_dma_param()
660 dma_chan = tspi->tx_dma_chan; in tegra_slink_deinit_dma_param()
661 dma_phys = tspi->tx_dma_phys; in tegra_slink_deinit_dma_param()
662 tspi->tx_dma_buf = NULL; in tegra_slink_deinit_dma_param()
663 tspi->tx_dma_chan = NULL; in tegra_slink_deinit_dma_param()
668 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); in tegra_slink_deinit_dma_param()
675 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); in tegra_slink_start_transfer_one()
683 bits_per_word = t->bits_per_word; in tegra_slink_start_transfer_one()
684 speed = t->speed_hz; in tegra_slink_start_transfer_one()
685 if (speed != tspi->cur_speed) { in tegra_slink_start_transfer_one()
686 clk_set_rate(tspi->clk, speed * 4); in tegra_slink_start_transfer_one()
687 tspi->cur_speed = speed; in tegra_slink_start_transfer_one()
690 tspi->cur_spi = spi; in tegra_slink_start_transfer_one()
691 tspi->cur_pos = 0; in tegra_slink_start_transfer_one()
692 tspi->cur_rx_pos = 0; in tegra_slink_start_transfer_one()
693 tspi->cur_tx_pos = 0; in tegra_slink_start_transfer_one()
694 tspi->curr_xfer = t; in tegra_slink_start_transfer_one()
697 command = tspi->command_reg; in tegra_slink_start_transfer_one()
699 command |= SLINK_BIT_LENGTH(bits_per_word - 1); in tegra_slink_start_transfer_one()
701 command2 = tspi->command2_reg; in tegra_slink_start_transfer_one()
704 tspi->cur_direction = 0; in tegra_slink_start_transfer_one()
705 if (t->rx_buf) { in tegra_slink_start_transfer_one()
707 tspi->cur_direction |= DATA_DIR_RX; in tegra_slink_start_transfer_one()
709 if (t->tx_buf) { in tegra_slink_start_transfer_one()
711 tspi->cur_direction |= DATA_DIR_TX; in tegra_slink_start_transfer_one()
720 tspi->command2_reg = command2; in tegra_slink_start_transfer_one()
723 tspi->command_reg = command; in tegra_slink_start_transfer_one()
741 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); in tegra_slink_setup()
746 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", in tegra_slink_setup()
747 spi->bits_per_word, in tegra_slink_setup()
748 spi->mode & SPI_CPOL ? "" : "~", in tegra_slink_setup()
749 spi->mode & SPI_CPHA ? "" : "~", in tegra_slink_setup()
750 spi->max_speed_hz); in tegra_slink_setup()
752 ret = pm_runtime_get_sync(tspi->dev); in tegra_slink_setup()
754 pm_runtime_put_noidle(tspi->dev); in tegra_slink_setup()
755 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); in tegra_slink_setup()
759 spin_lock_irqsave(&tspi->lock, flags); in tegra_slink_setup()
760 val = tspi->def_command_reg; in tegra_slink_setup()
761 if (spi->mode & SPI_CS_HIGH) in tegra_slink_setup()
762 val |= cs_pol_bit[spi->chip_select]; in tegra_slink_setup()
764 val &= ~cs_pol_bit[spi->chip_select]; in tegra_slink_setup()
765 tspi->def_command_reg = val; in tegra_slink_setup()
766 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); in tegra_slink_setup()
767 spin_unlock_irqrestore(&tspi->lock, flags); in tegra_slink_setup()
769 pm_runtime_put(tspi->dev); in tegra_slink_setup()
777 struct spi_device *spi = msg->spi; in tegra_slink_prepare_message()
781 tspi->command_reg = tspi->def_command_reg; in tegra_slink_prepare_message()
782 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE; in tegra_slink_prepare_message()
784 tspi->command2_reg = tspi->def_command2_reg; in tegra_slink_prepare_message()
785 tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select); in tegra_slink_prepare_message()
787 tspi->command_reg &= ~SLINK_MODES; in tegra_slink_prepare_message()
788 if (spi->mode & SPI_CPHA) in tegra_slink_prepare_message()
789 tspi->command_reg |= SLINK_CK_SDA; in tegra_slink_prepare_message()
791 if (spi->mode & SPI_CPOL) in tegra_slink_prepare_message()
792 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH; in tegra_slink_prepare_message()
794 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW; in tegra_slink_prepare_message()
806 reinit_completion(&tspi->xfer_completion); in tegra_slink_transfer_one()
809 dev_err(tspi->dev, in tegra_slink_transfer_one()
814 ret = wait_for_completion_timeout(&tspi->xfer_completion, in tegra_slink_transfer_one()
817 dev_err(tspi->dev, in tegra_slink_transfer_one()
819 return -EIO; in tegra_slink_transfer_one()
822 if (tspi->tx_status) in tegra_slink_transfer_one()
823 return tspi->tx_status; in tegra_slink_transfer_one()
824 if (tspi->rx_status) in tegra_slink_transfer_one()
825 return tspi->rx_status; in tegra_slink_transfer_one()
835 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); in tegra_slink_unprepare_message()
836 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); in tegra_slink_unprepare_message()
843 struct spi_transfer *t = tspi->curr_xfer; in handle_cpu_based_xfer()
846 spin_lock_irqsave(&tspi->lock, flags); in handle_cpu_based_xfer()
847 if (tspi->tx_status || tspi->rx_status || in handle_cpu_based_xfer()
848 (tspi->status_reg & SLINK_BSY)) { in handle_cpu_based_xfer()
849 dev_err(tspi->dev, in handle_cpu_based_xfer()
850 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg); in handle_cpu_based_xfer()
851 dev_err(tspi->dev, in handle_cpu_based_xfer()
852 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, in handle_cpu_based_xfer()
853 tspi->command2_reg, tspi->dma_control_reg); in handle_cpu_based_xfer()
854 reset_control_assert(tspi->rst); in handle_cpu_based_xfer()
856 reset_control_deassert(tspi->rst); in handle_cpu_based_xfer()
857 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
861 if (tspi->cur_direction & DATA_DIR_RX) in handle_cpu_based_xfer()
864 if (tspi->cur_direction & DATA_DIR_TX) in handle_cpu_based_xfer()
865 tspi->cur_pos = tspi->cur_tx_pos; in handle_cpu_based_xfer()
867 tspi->cur_pos = tspi->cur_rx_pos; in handle_cpu_based_xfer()
869 if (tspi->cur_pos == t->len) { in handle_cpu_based_xfer()
870 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
874 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); in handle_cpu_based_xfer()
877 spin_unlock_irqrestore(&tspi->lock, flags); in handle_cpu_based_xfer()
883 struct spi_transfer *t = tspi->curr_xfer; in handle_dma_based_xfer()
890 if (tspi->cur_direction & DATA_DIR_TX) { in handle_dma_based_xfer()
891 if (tspi->tx_status) { in handle_dma_based_xfer()
892 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
896 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT); in handle_dma_based_xfer()
898 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
899 dev_err(tspi->dev, "TxDma Xfer failed\n"); in handle_dma_based_xfer()
905 if (tspi->cur_direction & DATA_DIR_RX) { in handle_dma_based_xfer()
906 if (tspi->rx_status) { in handle_dma_based_xfer()
907 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
911 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT); in handle_dma_based_xfer()
913 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
914 dev_err(tspi->dev, "RxDma Xfer failed\n"); in handle_dma_based_xfer()
920 spin_lock_irqsave(&tspi->lock, flags); in handle_dma_based_xfer()
922 dev_err(tspi->dev, in handle_dma_based_xfer()
923 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg); in handle_dma_based_xfer()
924 dev_err(tspi->dev, in handle_dma_based_xfer()
925 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, in handle_dma_based_xfer()
926 tspi->command2_reg, tspi->dma_control_reg); in handle_dma_based_xfer()
927 reset_control_assert(tspi->rst); in handle_dma_based_xfer()
929 reset_control_assert(tspi->rst); in handle_dma_based_xfer()
930 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
931 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
935 if (tspi->cur_direction & DATA_DIR_RX) in handle_dma_based_xfer()
938 if (tspi->cur_direction & DATA_DIR_TX) in handle_dma_based_xfer()
939 tspi->cur_pos = tspi->cur_tx_pos; in handle_dma_based_xfer()
941 tspi->cur_pos = tspi->cur_rx_pos; in handle_dma_based_xfer()
943 if (tspi->cur_pos == t->len) { in handle_dma_based_xfer()
944 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
949 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, in handle_dma_based_xfer()
957 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
965 if (!tspi->is_curr_dma_xfer) in tegra_slink_isr_thread()
974 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS); in tegra_slink_isr()
975 if (tspi->cur_direction & DATA_DIR_TX) in tegra_slink_isr()
976 tspi->tx_status = tspi->status_reg & in tegra_slink_isr()
979 if (tspi->cur_direction & DATA_DIR_RX) in tegra_slink_isr()
980 tspi->rx_status = tspi->status_reg & in tegra_slink_isr()
996 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
997 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
1010 cdata = of_device_get_match_data(&pdev->dev); in tegra_slink_probe()
1012 master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); in tegra_slink_probe()
1014 dev_err(&pdev->dev, "master allocation failed\n"); in tegra_slink_probe()
1015 return -ENOMEM; in tegra_slink_probe()
1018 /* the spi->mode bits understood by this driver: */ in tegra_slink_probe()
1019 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in tegra_slink_probe()
1020 master->setup = tegra_slink_setup; in tegra_slink_probe()
1021 master->prepare_message = tegra_slink_prepare_message; in tegra_slink_probe()
1022 master->transfer_one = tegra_slink_transfer_one; in tegra_slink_probe()
1023 master->unprepare_message = tegra_slink_unprepare_message; in tegra_slink_probe()
1024 master->auto_runtime_pm = true; in tegra_slink_probe()
1025 master->num_chipselect = MAX_CHIP_SELECT; in tegra_slink_probe()
1029 tspi->master = master; in tegra_slink_probe()
1030 tspi->dev = &pdev->dev; in tegra_slink_probe()
1031 tspi->chip_data = cdata; in tegra_slink_probe()
1032 spin_lock_init(&tspi->lock); in tegra_slink_probe()
1034 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency", in tegra_slink_probe()
1035 &master->max_speed_hz)) in tegra_slink_probe()
1036 master->max_speed_hz = 25000000; /* 25MHz */ in tegra_slink_probe()
1040 dev_err(&pdev->dev, "No IO memory resource\n"); in tegra_slink_probe()
1041 ret = -ENODEV; in tegra_slink_probe()
1044 tspi->phys = r->start; in tegra_slink_probe()
1045 tspi->base = devm_ioremap_resource(&pdev->dev, r); in tegra_slink_probe()
1046 if (IS_ERR(tspi->base)) { in tegra_slink_probe()
1047 ret = PTR_ERR(tspi->base); in tegra_slink_probe()
1052 tspi->clk = devm_clk_get(&pdev->dev, NULL); in tegra_slink_probe()
1053 if (IS_ERR(tspi->clk)) { in tegra_slink_probe()
1054 ret = PTR_ERR(tspi->clk); in tegra_slink_probe()
1055 dev_err(&pdev->dev, "Can not get clock %d\n", ret); in tegra_slink_probe()
1058 ret = clk_prepare(tspi->clk); in tegra_slink_probe()
1060 dev_err(&pdev->dev, "Clock prepare failed %d\n", ret); in tegra_slink_probe()
1063 ret = clk_enable(tspi->clk); in tegra_slink_probe()
1065 dev_err(&pdev->dev, "Clock enable failed %d\n", ret); in tegra_slink_probe()
1070 tspi->irq = spi_irq; in tegra_slink_probe()
1071 ret = request_threaded_irq(tspi->irq, tegra_slink_isr, in tegra_slink_probe()
1073 dev_name(&pdev->dev), tspi); in tegra_slink_probe()
1075 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", in tegra_slink_probe()
1076 tspi->irq); in tegra_slink_probe()
1080 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); in tegra_slink_probe()
1081 if (IS_ERR(tspi->rst)) { in tegra_slink_probe()
1082 dev_err(&pdev->dev, "can not get reset\n"); in tegra_slink_probe()
1083 ret = PTR_ERR(tspi->rst); in tegra_slink_probe()
1087 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; in tegra_slink_probe()
1088 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; in tegra_slink_probe()
1096 tspi->max_buf_size = tspi->dma_buf_size; in tegra_slink_probe()
1097 init_completion(&tspi->tx_dma_complete); in tegra_slink_probe()
1098 init_completion(&tspi->rx_dma_complete); in tegra_slink_probe()
1100 init_completion(&tspi->xfer_completion); in tegra_slink_probe()
1102 pm_runtime_enable(&pdev->dev); in tegra_slink_probe()
1103 if (!pm_runtime_enabled(&pdev->dev)) { in tegra_slink_probe()
1104 ret = tegra_slink_runtime_resume(&pdev->dev); in tegra_slink_probe()
1109 ret = pm_runtime_get_sync(&pdev->dev); in tegra_slink_probe()
1111 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); in tegra_slink_probe()
1112 pm_runtime_put_noidle(&pdev->dev); in tegra_slink_probe()
1115 tspi->def_command_reg = SLINK_M_S; in tegra_slink_probe()
1116 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN; in tegra_slink_probe()
1117 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); in tegra_slink_probe()
1118 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); in tegra_slink_probe()
1119 pm_runtime_put(&pdev->dev); in tegra_slink_probe()
1121 master->dev.of_node = pdev->dev.of_node; in tegra_slink_probe()
1122 ret = devm_spi_register_master(&pdev->dev, master); in tegra_slink_probe()
1124 dev_err(&pdev->dev, "can not register to master err %d\n", ret); in tegra_slink_probe()
1130 pm_runtime_disable(&pdev->dev); in tegra_slink_probe()
1131 if (!pm_runtime_status_suspended(&pdev->dev)) in tegra_slink_probe()
1132 tegra_slink_runtime_suspend(&pdev->dev); in tegra_slink_probe()
1139 clk_disable(tspi->clk); in tegra_slink_probe()
1141 clk_unprepare(tspi->clk); in tegra_slink_probe()
1152 free_irq(tspi->irq, tspi); in tegra_slink_remove()
1154 clk_disable(tspi->clk); in tegra_slink_remove()
1155 clk_unprepare(tspi->clk); in tegra_slink_remove()
1157 if (tspi->tx_dma_chan) in tegra_slink_remove()
1160 if (tspi->rx_dma_chan) in tegra_slink_remove()
1163 pm_runtime_disable(&pdev->dev); in tegra_slink_remove()
1164 if (!pm_runtime_status_suspended(&pdev->dev)) in tegra_slink_remove()
1165 tegra_slink_runtime_suspend(&pdev->dev); in tegra_slink_remove()
1190 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND); in tegra_slink_resume()
1191 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2); in tegra_slink_resume()
1206 clk_disable_unprepare(tspi->clk); in tegra_slink_runtime_suspend()
1216 ret = clk_prepare_enable(tspi->clk); in tegra_slink_runtime_resume()
1218 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); in tegra_slink_runtime_resume()
1231 .name = "spi-tegra-slink",
1240 MODULE_ALIAS("platform:spi-tegra-slink");
1241 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");