Lines Matching +full:36 +full:- +full:41
1 /* SPDX-License-Identifier: GPL-2.0 */
40 #define CLK_MOUT_SCLK_MMC0_C 36
45 #define CLK_MOUT_SCLK_UART2 41
241 #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36
246 #define CLK_MOUT_SCLK_DSIM0_B 41
437 #define CLK_SCLK_UART0 36
442 #define CLK_PCLK_SCI 41
509 #define CLK_SCLK_SECKEY 36
514 #define CLK_SCLK_OTP_CON 41
554 #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36
692 #define CLK_DIV_PCLK_DISP 36
695 #define CLK_ACLK_DECON 41
814 #define CLK_PCLK_TIMER 36
819 #define CLK_SCLK_JTAG_TCK 41
979 #define CLK_PCLK_DBG_CSSYS 36
1107 #define CLK_ACLK_SMMU_SCALERC 36
1112 #define CLK_ACLK_BTS_DIS1 41
1190 #define CLK_DIV_ACLK_LITE_B 36
1195 #define CLK_DIV_PCLK_3AA1 41
1329 #define CLK_ACLK_ASYNCAXIS_CA5 36
1334 #define CLK_ACLK_ASYNCAXIM_ISP3P 41
1413 #define IMEM_NR_CLK 36