Lines Matching +full:42 +full:- +full:47
1 /* SPDX-License-Identifier: GPL-2.0 */
46 #define CLK_MOUT_SCLK_UART1 42
51 #define CLK_MOUT_ACLK_MFC_400_C 47
247 #define CLK_MOUT_SCLK_DSIM0_A 42
249 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47
443 #define CLK_PCLK_GPIO_FINGER 42
448 #define CLK_PCLK_I2S1 47
516 #define PERIS_NR_CLK 42
696 #define CLK_ACLK_SMMU_TV1X 42
701 #define CLK_ACLK_BTS_DECON_TV_M2 47
820 #define CLK_SCLK_SLIMBUS_CLKIN 42
825 #define CLK_SCLK_AUD_I2S 47
1113 #define CLK_ACLK_BTS_DIS0 42
1118 #define CLK_PCLK_SMMU_3DNR 47
1196 #define CLK_DIV_ACLK_3AA1 42
1201 #define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47
1335 #define CLK_ACLK_ASYNCAXIS_ISP3P 42
1340 #define CLK_ACLK_AHB2APB_ISP5P 47