Lines Matching +full:1 +full:c00
48 #address-cells = <1>;
49 #size-cells = <1>;
79 #address-cells = <1>;
93 timer@1 {
95 reg = <1>;
101 #address-cells = <1>;
123 #address-cells = <1>;
144 timers5: timers@40000c00 {
145 #address-cells = <1>;
167 #address-cells = <1>;
183 #address-cells = <1>;
199 #address-cells = <1>;
220 timers13: timers@40001c00 {
251 clocks = <&rcc 1 CLK_RTC>;
252 assigned-clocks = <&rcc 1 CLK_RTC>;
253 assigned-clock-parents = <&rcc 1 CLK_LSE>;
255 interrupts = <17 1>;
281 clocks = <&rcc 1 CLK_USART2>;
289 clocks = <&rcc 1 CLK_USART3>;
293 usart4: serial@40004c00 {
297 clocks = <&rcc 1 CLK_UART4>;
305 clocks = <&rcc 1 CLK_UART5>;
315 clocks = <&rcc 1 CLK_I2C1>;
316 #address-cells = <1>;
327 clocks = <&rcc 1 CLK_I2C2>;
328 #address-cells = <1>;
333 i2c3: i2c@40005c00 {
339 clocks = <&rcc 1 CLK_I2C3>;
340 #address-cells = <1>;
351 clocks = <&rcc 1 CLK_I2C4>;
352 #address-cells = <1>;
387 cec: cec@40006c00 {
391 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
400 clocks = <&rcc 1 CLK_UART7>;
404 usart8: serial@40007c00 {
408 clocks = <&rcc 1 CLK_UART8>;
413 #address-cells = <1>;
435 #address-cells = <1>;
460 clocks = <&rcc 1 CLK_USART1>;
468 clocks = <&rcc 1 CLK_USART6>;
472 sdio2: mmc@40011c00 {
483 sdio1: mmc@40012c00 {
499 exti: interrupt-controller@40013c00 {
504 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
508 #address-cells = <1>;
562 clocks = <&rcc 1 CLK_LCD>;
580 #reset-cells = <1>;
586 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
647 clocks = <&rcc 1 0>;