26  * called (PCC) Platform Communication Channel. This is a generic mailbox like
28  * See drivers/mailbox/pcc.c for details on PCC.
30  * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
52 	bool pending_pcc_write_cmd;	/* Any pending/batched PCC write cmds? */
53 	bool platform_owns_pcc;		/* Ownership of PCC subspace */
54 	unsigned int pcc_write_cnt;	/* Running count of PCC write commands */
57 	 * Lock to provide controlled access to the PCC channel.
61 	 * before reading or writing to PCC subspace
80 /* Array to represent the PCC channel per subspace ID */
88  * include the type of register (e.g. PCC, System IO, FFH etc.)
94 /* pcc mapped address + header size + offset within PCC subspace */
98 /* Check if a CPC register is in PCC */
126  * to PCC commands. Keeping it high enough to cover emulators where
212 	 * Poll PCC status register every 3us(delay_us) for maximum of  in check_pcc_chan()
213 	 * deadline_us(timeout_us) until PCC command complete bit is set(cond)  in check_pcc_chan()
226 		pr_err("PCC check channel failed for ss: %d. ret=%d\n",  in check_pcc_chan()
233  * This function transfers the ownership of the PCC to the platform
246 	 * the channel before writing to PCC space  in send_pcc_cmd()
291 				pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",  in send_pcc_cmd()
313 		pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",  in send_pcc_cmd()
318 	/* wait for completion and check for PCC error bit */  in send_pcc_cmd()
537 			pr_err("Failed to find PCC channel for subspace %d\n",  in register_pcc_channel()
558 			pr_err("Failed to ioremap PCC comm region mem for %d\n",  in register_pcc_channel()
597  * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
598  * @pcc_ss_id: PCC Subspace index as in the PCC client ACPI package.
631  *      ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)},	// Highest Performance
632  *      ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)},	// Nominal Performance
633  *      ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)},	// Lowest Nonlinear Performance
634  *      ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)},	// Lowest Performance
635  *      ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)},	// Guaranteed Performance Register
636  *      ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)},	// Desired Performance Register
643  * e.g. a sample PCC entry has the following encoding:
646  *      PCC,	// AddressSpaceKeyword
762 			 * The PCC Subspace index is encoded inside  in acpi_cppc_processor_probe()
763 			 * the CPC table entries. The same PCC index  in acpi_cppc_processor_probe()
764 			 * will be used for all the PCC entries,  in acpi_cppc_processor_probe()
773 					pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",  in acpi_cppc_processor_probe()
816 					/* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */  in acpi_cppc_processor_probe()
852 	/* Register PCC channel once for all PCC subspace ID. */  in acpi_cppc_processor_probe()
976  * as fast as possible. We have already mapped the PCC subspace during init, so
1032 		pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",  in cpc_read()
1084 		pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",  in cpc_write()
1201 	/* Are any of the regs PCC ?*/  in cppc_get_perf_caps()
1212 		/* Ring doorbell once to update PCC subspace */  in cppc_get_perf_caps()
1261  * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
1264  * One of the choices is PCC regions, which can have a high access latency. This
1267  * Return: true if any of the counters are in PCC regions, false otherwise
1336 	/* Are any of the regs PCC ?*/  in cppc_get_perf_ctrs()
1346 		/* Ring doorbell once to update PCC subspace */  in cppc_get_perf_ctrs()
1424 		/* after writing CPC, transfer the ownership of PCC to platform */  in cppc_set_epp_perf()
1429 		pr_debug("_CPC in PCC is not supported\n");  in cppc_set_epp_perf()
1520 		/* after writing CPC, transfer the ownership of PCC to platform */  in cppc_set_auto_sel()
1525 		pr_debug("_CPC in PCC is not supported\n");  in cppc_set_auto_sel()
1567 		/* after writing CPC, transfer the ownership of PCC to platfrom */  in cppc_set_enable()
1623 		 * Update the pending_write to make sure a PCC CMD_READ will not  in cppc_set_perf()
1646 	 * This is Phase-II where we transfer the ownership of PCC to Platform  in cppc_set_perf()
1661 	 * PCC ownership to the platform, then one of the following will be TRUE  in cppc_set_perf()
1669 	 *     3. Some other CPU executing pcc CMD_READ has stolen the  in cppc_set_perf()
1681 	 * doorbell and transferred the ownership of PCC to platform. So this  in cppc_set_perf()
1683 	 * triggering the doorbell it makes sure that the PCC channel ownership  in cppc_set_perf()
1686 	 * there was a pcc CMD_READ waiting on down_write and it steals the lock  in cppc_set_perf()
1687 	 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this  in cppc_set_perf()
1716  * on the number and frequency of PCC commands the platform can handle.