Lines Matching +full:pll +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
49 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
50 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
55 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
56 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
57 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
58 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
59 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
60 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
61 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
256 /* TRION PLL specific settings and offsets */
260 /* LUCID PLL specific settings and offsets */
263 /* LUCID 5LPE PLL specific settings and offsets */
269 /* LUCID EVO PLL specific settings and offsets */
275 /* ZONDA PLL specific */
281 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
284 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
292 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
298 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
300 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
304 for (count = 200; count > 0; count--) { in wait_for_pll()
305 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
317 return -ETIMEDOUT; in wait_for_pll()
320 #define wait_for_pll_enable_active(pll) \ argument
321 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
323 #define wait_for_pll_enable_lock(pll) \ argument
324 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
326 #define wait_for_zonda_pll_freq_lock(pll) \ argument
327 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
329 #define wait_for_pll_disable(pll) \ argument
330 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
332 #define wait_for_pll_offline(pll) \ argument
333 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
335 #define wait_for_pll_update(pll) \ argument
336 wait_for_pll(pll, PLL_UPDATE, 1, "update")
338 #define wait_for_pll_update_ack_set(pll) \ argument
339 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
341 #define wait_for_pll_update_ack_clear(pll) \ argument
342 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
351 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_alpha_pll_configure() argument
356 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_alpha_pll_configure()
357 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_alpha_pll_configure()
358 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_alpha_pll_configure()
360 if (pll_has_64bit_config(pll)) in clk_alpha_pll_configure()
361 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_alpha_pll_configure()
362 config->config_ctl_hi_val); in clk_alpha_pll_configure()
364 if (pll_alpha_width(pll) > 32) in clk_alpha_pll_configure()
365 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_alpha_pll_configure()
367 val = config->main_output_mask; in clk_alpha_pll_configure()
368 val |= config->aux_output_mask; in clk_alpha_pll_configure()
369 val |= config->aux2_output_mask; in clk_alpha_pll_configure()
370 val |= config->early_output_mask; in clk_alpha_pll_configure()
371 val |= config->pre_div_val; in clk_alpha_pll_configure()
372 val |= config->post_div_val; in clk_alpha_pll_configure()
373 val |= config->vco_val; in clk_alpha_pll_configure()
374 val |= config->alpha_en_mask; in clk_alpha_pll_configure()
375 val |= config->alpha_mode_mask; in clk_alpha_pll_configure()
377 mask = config->main_output_mask; in clk_alpha_pll_configure()
378 mask |= config->aux_output_mask; in clk_alpha_pll_configure()
379 mask |= config->aux2_output_mask; in clk_alpha_pll_configure()
380 mask |= config->early_output_mask; in clk_alpha_pll_configure()
381 mask |= config->pre_div_mask; in clk_alpha_pll_configure()
382 mask |= config->post_div_mask; in clk_alpha_pll_configure()
383 mask |= config->vco_mask; in clk_alpha_pll_configure()
385 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_alpha_pll_configure()
387 if (config->test_ctl_mask) in clk_alpha_pll_configure()
388 regmap_update_bits(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
389 config->test_ctl_mask, in clk_alpha_pll_configure()
390 config->test_ctl_val); in clk_alpha_pll_configure()
392 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
393 config->test_ctl_val); in clk_alpha_pll_configure()
395 if (config->test_ctl_hi_mask) in clk_alpha_pll_configure()
396 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
397 config->test_ctl_hi_mask, in clk_alpha_pll_configure()
398 config->test_ctl_hi_val); in clk_alpha_pll_configure()
400 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
401 config->test_ctl_hi_val); in clk_alpha_pll_configure()
403 if (pll->flags & SUPPORTS_FSM_MODE) in clk_alpha_pll_configure()
404 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_alpha_pll_configure()
411 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_enable() local
414 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_enable()
420 if (pll->flags & SUPPORTS_OFFLINE_REQ) in clk_alpha_pll_hwfsm_enable()
423 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); in clk_alpha_pll_hwfsm_enable()
430 return wait_for_pll_enable_active(pll); in clk_alpha_pll_hwfsm_enable()
436 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_disable() local
439 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_disable()
443 if (pll->flags & SUPPORTS_OFFLINE_REQ) { in clk_alpha_pll_hwfsm_disable()
444 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
449 ret = wait_for_pll_offline(pll); in clk_alpha_pll_hwfsm_disable()
455 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
460 wait_for_pll_disable(pll); in clk_alpha_pll_hwfsm_disable()
466 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in pll_is_enabled() local
469 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in pll_is_enabled()
489 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_enable() local
493 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_enable()
497 /* If in FSM mode, just vote for it */ in clk_alpha_pll_enable()
502 return wait_for_pll_enable_active(pll); in clk_alpha_pll_enable()
509 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
516 * de-asserting the reset. in clk_alpha_pll_enable()
521 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
526 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_enable()
530 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
541 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_disable() local
544 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_disable()
548 /* If in FSM mode, just unvote it */ in clk_alpha_pll_disable()
555 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
562 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
600 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) in alpha_pll_find_vco() argument
602 const struct pll_vco *v = pll->vco_table; in alpha_pll_find_vco()
603 const struct pll_vco *end = v + pll->num_vco; in alpha_pll_find_vco()
606 if (rate >= v->min_freq && rate <= v->max_freq) in alpha_pll_find_vco()
617 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_recalc_rate() local
618 u32 alpha_width = pll_alpha_width(pll); in clk_alpha_pll_recalc_rate()
620 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_alpha_pll_recalc_rate()
622 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_recalc_rate()
624 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); in clk_alpha_pll_recalc_rate()
626 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_recalc_rate()
630 a = low & GENMASK(alpha_width - 1, 0); in clk_alpha_pll_recalc_rate()
634 a >>= alpha_width - ALPHA_BITWIDTH; in clk_alpha_pll_recalc_rate()
641 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) in __clk_alpha_pll_update_latch() argument
644 u32 mode; in __clk_alpha_pll_update_latch() local
646 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); in __clk_alpha_pll_update_latch()
648 /* Latch the input to the PLL */ in __clk_alpha_pll_update_latch()
649 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in __clk_alpha_pll_update_latch()
656 * PLL will latch the new L, Alpha and freq control word. in __clk_alpha_pll_update_latch()
657 * PLL will respond by raising PLL_ACK_LATCH output when new programming in __clk_alpha_pll_update_latch()
658 * has been latched in and PLL is being updated. When in __clk_alpha_pll_update_latch()
660 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. in __clk_alpha_pll_update_latch()
662 if (mode & PLL_UPDATE_BYPASS) { in __clk_alpha_pll_update_latch()
663 ret = wait_for_pll_update_ack_set(pll); in __clk_alpha_pll_update_latch()
667 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); in __clk_alpha_pll_update_latch()
669 ret = wait_for_pll_update(pll); in __clk_alpha_pll_update_latch()
674 ret = wait_for_pll_update_ack_clear(pll); in __clk_alpha_pll_update_latch()
678 /* Wait for PLL output to stabilize */ in __clk_alpha_pll_update_latch()
684 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, in clk_alpha_pll_update_latch() argument
687 if (!is_enabled(&pll->clkr.hw) || in clk_alpha_pll_update_latch()
688 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) in clk_alpha_pll_update_latch()
691 return __clk_alpha_pll_update_latch(pll); in clk_alpha_pll_update_latch()
698 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __clk_alpha_pll_set_rate() local
700 u32 l, alpha_width = pll_alpha_width(pll); in __clk_alpha_pll_set_rate()
704 vco = alpha_pll_find_vco(pll, rate); in __clk_alpha_pll_set_rate()
705 if (pll->vco_table && !vco) { in __clk_alpha_pll_set_rate()
706 pr_err("%s: alpha pll not in a valid vco range\n", in __clk_alpha_pll_set_rate()
708 return -EINVAL; in __clk_alpha_pll_set_rate()
711 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __clk_alpha_pll_set_rate()
714 a <<= alpha_width - ALPHA_BITWIDTH; in __clk_alpha_pll_set_rate()
717 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); in __clk_alpha_pll_set_rate()
719 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __clk_alpha_pll_set_rate()
722 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
724 vco->val << PLL_VCO_SHIFT); in __clk_alpha_pll_set_rate()
727 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
730 return clk_alpha_pll_update_latch(pll, is_enabled); in __clk_alpha_pll_set_rate()
750 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_round_rate() local
751 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_round_rate()
756 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_alpha_pll_round_rate()
759 min_freq = pll->vco_table[0].min_freq; in clk_alpha_pll_round_rate()
760 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_alpha_pll_round_rate()
770 * of [-0.5, 0.5). in alpha_huayra_pll_calc_rate()
772 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_calc_rate()
773 l -= 1; in alpha_huayra_pll_calc_rate()
802 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value in alpha_huayra_pll_round_rate()
805 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_round_rate()
816 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_recalc_rate() local
819 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_huayra_recalc_rate()
820 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_recalc_rate()
823 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); in alpha_pll_huayra_recalc_rate()
831 * M is a signed number (-128 to 127) and N is unsigned in alpha_pll_huayra_recalc_rate()
832 * (0 to 255). M/N has to be within +/-0.5. in alpha_pll_huayra_recalc_rate()
835 * range [-0.5, 0.5). in alpha_pll_huayra_recalc_rate()
849 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { in alpha_pll_huayra_recalc_rate()
850 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; in alpha_pll_huayra_recalc_rate()
853 rate -= tmp; in alpha_pll_huayra_recalc_rate()
869 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_set_rate() local
874 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_set_rate()
877 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); in alpha_pll_huayra_set_rate()
880 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, in alpha_pll_huayra_set_rate()
887 return -EBUSY; in alpha_pll_huayra_set_rate()
890 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
893 return wait_for_pll_enable_lock(pll); in alpha_pll_huayra_set_rate()
896 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
897 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_huayra_set_rate()
900 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
903 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
917 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, in trion_pll_is_enabled() argument
923 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); in trion_pll_is_enabled()
924 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in trion_pll_is_enabled()
933 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_is_enabled() local
935 return trion_pll_is_enabled(pll, pll->clkr.regmap); in clk_trion_pll_is_enabled()
940 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_enable() local
941 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_enable()
945 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_enable()
949 /* If in FSM mode, just vote for it */ in clk_trion_pll_enable()
954 return wait_for_pll_enable_active(pll); in clk_trion_pll_enable()
957 /* Set operation mode to RUN */ in clk_trion_pll_enable()
958 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_trion_pll_enable()
960 ret = wait_for_pll_enable_lock(pll); in clk_trion_pll_enable()
964 /* Enable the PLL outputs */ in clk_trion_pll_enable()
965 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_enable()
970 /* Enable the global PLL outputs */ in clk_trion_pll_enable()
971 return regmap_update_bits(regmap, PLL_MODE(pll), in clk_trion_pll_enable()
977 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_disable() local
978 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_disable()
982 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_disable()
986 /* If in FSM mode, just unvote it */ in clk_trion_pll_disable()
992 /* Disable the global PLL output */ in clk_trion_pll_disable()
993 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
997 /* Disable the PLL outputs */ in clk_trion_pll_disable()
998 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_disable()
1003 /* Place the PLL mode in STANDBY */ in clk_trion_pll_disable()
1004 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_disable()
1005 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_disable()
1011 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_recalc_rate() local
1012 u32 l, frac, alpha_width = pll_alpha_width(pll); in clk_trion_pll_recalc_rate()
1014 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_trion_pll_recalc_rate()
1015 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); in clk_trion_pll_recalc_rate()
1070 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_recalc_rate() local
1073 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_recalc_rate()
1076 ctl &= PLL_POST_DIV_MASK(pll); in clk_alpha_pll_postdiv_recalc_rate()
1101 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_rate() local
1104 if (pll->width == 2) in clk_alpha_pll_postdiv_round_rate()
1110 pll->width, CLK_DIVIDER_POWER_OF_TWO); in clk_alpha_pll_postdiv_round_rate()
1117 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_ro_rate() local
1120 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_round_ro_rate()
1123 ctl &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_round_ro_rate()
1135 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_set_rate() local
1138 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ in clk_alpha_pll_postdiv_set_rate()
1139 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; in clk_alpha_pll_postdiv_set_rate()
1141 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_set_rate()
1142 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_alpha_pll_postdiv_set_rate()
1159 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_fabia_pll_configure() argument
1164 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_fabia_pll_configure()
1165 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); in clk_fabia_pll_configure()
1166 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_fabia_pll_configure()
1167 config->config_ctl_val); in clk_fabia_pll_configure()
1168 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_fabia_pll_configure()
1169 config->config_ctl_hi_val); in clk_fabia_pll_configure()
1170 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_fabia_pll_configure()
1171 config->user_ctl_val); in clk_fabia_pll_configure()
1172 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_fabia_pll_configure()
1173 config->user_ctl_hi_val); in clk_fabia_pll_configure()
1174 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_fabia_pll_configure()
1175 config->test_ctl_val); in clk_fabia_pll_configure()
1176 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_fabia_pll_configure()
1177 config->test_ctl_hi_val); in clk_fabia_pll_configure()
1179 if (config->post_div_mask) { in clk_fabia_pll_configure()
1180 mask = config->post_div_mask; in clk_fabia_pll_configure()
1181 val = config->post_div_val; in clk_fabia_pll_configure()
1182 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_fabia_pll_configure()
1185 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) in clk_fabia_pll_configure()
1186 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, in clk_fabia_pll_configure()
1189 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_fabia_pll_configure()
1192 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_fabia_pll_configure()
1199 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_enable() local
1201 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_enable()
1203 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_enable()
1207 /* If in FSM mode, just vote for it */ in alpha_pll_fabia_enable()
1212 return wait_for_pll_enable_active(pll); in alpha_pll_fabia_enable()
1215 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in alpha_pll_fabia_enable()
1219 /* Skip If PLL is already running */ in alpha_pll_fabia_enable()
1223 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_enable()
1227 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_enable()
1231 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, in alpha_pll_fabia_enable()
1236 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_fabia_enable()
1240 ret = wait_for_pll_enable_lock(pll); in alpha_pll_fabia_enable()
1244 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in alpha_pll_fabia_enable()
1249 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, in alpha_pll_fabia_enable()
1256 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_disable() local
1258 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_disable()
1260 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_disable()
1264 /* If in FSM mode, just unvote it */ in alpha_pll_fabia_disable()
1270 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_disable()
1275 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_fabia_disable()
1279 /* Place the PLL in STANDBY */ in alpha_pll_fabia_disable()
1280 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_disable()
1286 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_recalc_rate() local
1287 u32 l, frac, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_recalc_rate()
1289 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_fabia_recalc_rate()
1290 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); in alpha_pll_fabia_recalc_rate()
1307 return -EINVAL; in alpha_pll_check_rate_margin()
1316 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_set_rate() local
1317 u32 l, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_set_rate()
1328 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_fabia_set_rate()
1329 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); in alpha_pll_fabia_set_rate()
1331 return __clk_alpha_pll_update_latch(pll); in alpha_pll_fabia_set_rate()
1336 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_prepare() local
1340 u32 cal_l, val, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_prepare()
1345 /* Check if calibration needs to be done i.e. PLL is in reset */ in alpha_pll_fabia_prepare()
1346 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_prepare()
1354 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in alpha_pll_fabia_prepare()
1356 pr_err("%s: alpha pll not in a valid vco range\n", name); in alpha_pll_fabia_prepare()
1357 return -EINVAL; in alpha_pll_fabia_prepare()
1360 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + in alpha_pll_fabia_prepare()
1361 pll->vco_table[0].max_freq) * 54, 100); in alpha_pll_fabia_prepare()
1365 return -EINVAL; in alpha_pll_fabia_prepare()
1374 /* Setup PLL for calibration frequency */ in alpha_pll_fabia_prepare()
1375 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); in alpha_pll_fabia_prepare()
1377 /* Bringup the PLL at calibration frequency */ in alpha_pll_fabia_prepare()
1380 pr_err("%s: alpha pll calibration failed\n", name); in alpha_pll_fabia_prepare()
1412 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_recalc_rate() local
1416 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_alpha_pll_postdiv_fabia_recalc_rate()
1420 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1421 val &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1423 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1424 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1425 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1436 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_recalc_rate() local
1437 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_recalc_rate()
1440 regmap_read(regmap, PLL_USER_CTL(pll), &val); in clk_trion_pll_postdiv_recalc_rate()
1442 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1443 val &= PLL_POST_DIV_MASK(pll); in clk_trion_pll_postdiv_recalc_rate()
1445 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_recalc_rate()
1446 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1447 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1459 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_round_rate() local
1461 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1462 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_trion_pll_postdiv_round_rate()
1469 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_set_rate() local
1470 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_set_rate()
1474 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_set_rate()
1475 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1476 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1481 return regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_postdiv_set_rate()
1482 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_trion_pll_postdiv_set_rate()
1496 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_round_rate() local
1498 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1499 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_alpha_pll_postdiv_fabia_round_rate()
1505 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_set_rate() local
1509 * If the PLL is in FSM mode, then treat set_rate callback as a in clk_alpha_pll_postdiv_fabia_set_rate()
1510 * no-operation. in clk_alpha_pll_postdiv_fabia_set_rate()
1512 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_postdiv_fabia_set_rate()
1520 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_set_rate()
1521 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1522 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
1527 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_fabia_set_rate()
1528 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1529 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1540 * clk_trion_pll_configure - configure the trion pll
1542 * @pll: clk alpha pll
1544 * @config: configuration to apply for pll
1546 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_trion_pll_configure() argument
1550 * If the bootloader left the PLL enabled it's likely that there are in clk_trion_pll_configure()
1551 * RCGs that will lock up if we disable the PLL below. in clk_trion_pll_configure()
1553 if (trion_pll_is_enabled(pll, regmap)) { in clk_trion_pll_configure()
1554 pr_debug("Trion PLL is already enabled, skipping configuration\n"); in clk_trion_pll_configure()
1558 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_trion_pll_configure()
1559 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_trion_pll_configure()
1560 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_trion_pll_configure()
1561 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_trion_pll_configure()
1562 config->config_ctl_val); in clk_trion_pll_configure()
1563 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_trion_pll_configure()
1564 config->config_ctl_hi_val); in clk_trion_pll_configure()
1565 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_trion_pll_configure()
1566 config->config_ctl_hi1_val); in clk_trion_pll_configure()
1567 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_trion_pll_configure()
1568 config->user_ctl_val); in clk_trion_pll_configure()
1569 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_trion_pll_configure()
1570 config->user_ctl_hi_val); in clk_trion_pll_configure()
1571 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_trion_pll_configure()
1572 config->user_ctl_hi1_val); in clk_trion_pll_configure()
1573 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_trion_pll_configure()
1574 config->test_ctl_val); in clk_trion_pll_configure()
1575 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_trion_pll_configure()
1576 config->test_ctl_hi_val); in clk_trion_pll_configure()
1577 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_trion_pll_configure()
1578 config->test_ctl_hi1_val); in clk_trion_pll_configure()
1580 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_trion_pll_configure()
1583 /* Disable PLL output */ in clk_trion_pll_configure()
1584 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_configure()
1586 /* Set operation mode to OFF */ in clk_trion_pll_configure()
1587 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_configure()
1589 /* Place the PLL in STANDBY mode */ in clk_trion_pll_configure()
1590 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_configure()
1595 * The TRION PLL requires a power-on self-calibration which happens when the
1596 * PLL comes out of reset. Calibrate in case it is not completed.
1600 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_prepare() local
1605 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); in __alpha_pll_trion_prepare()
1630 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_set_rate() local
1632 u32 val, l, alpha_width = pll_alpha_width(pll); in __alpha_pll_trion_set_rate()
1642 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __alpha_pll_trion_set_rate()
1643 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __alpha_pll_trion_set_rate()
1645 /* Latch the PLL input */ in __alpha_pll_trion_set_rate()
1646 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); in __alpha_pll_trion_set_rate()
1652 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in __alpha_pll_trion_set_rate()
1654 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); in __alpha_pll_trion_set_rate()
1655 return -EINVAL; in __alpha_pll_trion_set_rate()
1659 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); in __alpha_pll_trion_set_rate()
1664 ret = wait_for_pll_enable_lock(pll); in __alpha_pll_trion_set_rate()
1669 /* Wait for PLL output to stabilize */ in __alpha_pll_trion_set_rate()
1709 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_agera_pll_configure() argument
1712 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_agera_pll_configure()
1713 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_agera_pll_configure()
1714 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_agera_pll_configure()
1715 config->user_ctl_val); in clk_agera_pll_configure()
1716 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_agera_pll_configure()
1717 config->config_ctl_val); in clk_agera_pll_configure()
1718 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_agera_pll_configure()
1719 config->config_ctl_hi_val); in clk_agera_pll_configure()
1720 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_agera_pll_configure()
1721 config->test_ctl_val); in clk_agera_pll_configure()
1722 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_agera_pll_configure()
1723 config->test_ctl_hi_val); in clk_agera_pll_configure()
1730 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_agera_set_rate() local
1731 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_agera_set_rate()
1742 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_agera_set_rate()
1743 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_agera_set_rate()
1746 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_agera_set_rate()
1763 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_enable() local
1767 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_enable()
1771 /* If in FSM mode, just vote for it */ in alpha_pll_lucid_5lpe_enable()
1776 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1779 /* Check if PLL is already enabled, return if enabled */ in alpha_pll_lucid_5lpe_enable()
1780 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); in alpha_pll_lucid_5lpe_enable()
1784 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_5lpe_enable()
1788 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_5lpe_enable()
1790 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1794 /* Enable the PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1795 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_5lpe_enable()
1799 /* Enable the global PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1800 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_5lpe_enable()
1805 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_disable() local
1809 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_disable()
1813 /* If in FSM mode, just unvote it */ in alpha_pll_lucid_5lpe_disable()
1819 /* Disable the global PLL output */ in alpha_pll_lucid_5lpe_disable()
1820 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_lucid_5lpe_disable()
1824 /* Disable the PLL outputs */ in alpha_pll_lucid_5lpe_disable()
1825 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_lucid_5lpe_disable()
1829 /* Place the PLL mode in STANDBY */ in alpha_pll_lucid_5lpe_disable()
1830 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_lucid_5lpe_disable()
1834 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1835 * when the PLL comes out of reset. Calibrate in case it is not completed.
1839 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_prepare() local
1845 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_lucid_5lpe_prepare()
1851 return -EINVAL; in alpha_pll_lucid_5lpe_prepare()
1874 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in __clk_lucid_pll_postdiv_set_rate() local
1875 struct regmap *regmap = pll->clkr.regmap; in __clk_lucid_pll_postdiv_set_rate()
1880 * If the PLL is in FSM mode, then treat set_rate callback as a in __clk_lucid_pll_postdiv_set_rate()
1881 * no-operation. in __clk_lucid_pll_postdiv_set_rate()
1883 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in __clk_lucid_pll_postdiv_set_rate()
1890 if (!pll->post_div_table) { in __clk_lucid_pll_postdiv_set_rate()
1891 pr_err("Missing the post_div_table for the %s PLL\n", in __clk_lucid_pll_postdiv_set_rate()
1892 clk_hw_get_name(&pll->clkr.hw)); in __clk_lucid_pll_postdiv_set_rate()
1893 return -EINVAL; in __clk_lucid_pll_postdiv_set_rate()
1897 for (i = 0; i < pll->num_post_div; i++) { in __clk_lucid_pll_postdiv_set_rate()
1898 if (pll->post_div_table[i].div == div) { in __clk_lucid_pll_postdiv_set_rate()
1899 val = pll->post_div_table[i].val; in __clk_lucid_pll_postdiv_set_rate()
1904 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
1905 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_lucid_pll_postdiv_set_rate()
1906 mask, val << pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
1942 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_zonda_pll_configure() argument
1945 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_zonda_pll_configure()
1946 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_zonda_pll_configure()
1947 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_zonda_pll_configure()
1948 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_zonda_pll_configure()
1949 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_zonda_pll_configure()
1950 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_zonda_pll_configure()
1951 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_zonda_pll_configure()
1952 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_zonda_pll_configure()
1953 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_zonda_pll_configure()
1954 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_zonda_pll_configure()
1955 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_zonda_pll_configure()
1957 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); in clk_zonda_pll_configure()
1959 /* Disable PLL output */ in clk_zonda_pll_configure()
1960 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_configure()
1962 /* Set operation mode to OFF */ in clk_zonda_pll_configure()
1963 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_zonda_pll_configure()
1965 /* Place the PLL in STANDBY mode */ in clk_zonda_pll_configure()
1966 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_configure()
1972 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_enable() local
1973 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_enable()
1977 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_enable()
1979 /* If in FSM mode, just vote for it */ in clk_zonda_pll_enable()
1984 return wait_for_pll_enable_active(pll); in clk_zonda_pll_enable()
1987 /* Get the PLL out of bypass mode */ in clk_zonda_pll_enable()
1988 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_zonda_pll_enable()
1992 * de-asserting the reset. in clk_zonda_pll_enable()
1996 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_enable()
1998 /* Set operation mode to RUN */ in clk_zonda_pll_enable()
1999 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_zonda_pll_enable()
2001 regmap_read(regmap, PLL_TEST_CTL(pll), &val); in clk_zonda_pll_enable()
2003 /* If cfa mode then poll for freq lock */ in clk_zonda_pll_enable()
2005 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_enable()
2007 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_enable()
2011 /* Enable the PLL outputs */ in clk_zonda_pll_enable()
2012 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); in clk_zonda_pll_enable()
2014 /* Enable the global PLL outputs */ in clk_zonda_pll_enable()
2015 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_zonda_pll_enable()
2022 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_disable() local
2023 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_disable()
2026 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_disable()
2028 /* If in FSM mode, just unvote it */ in clk_zonda_pll_disable()
2034 /* Disable the global PLL output */ in clk_zonda_pll_disable()
2035 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_disable()
2037 /* Disable the PLL outputs */ in clk_zonda_pll_disable()
2038 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); in clk_zonda_pll_disable()
2040 /* Put the PLL in bypass and reset */ in clk_zonda_pll_disable()
2041 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); in clk_zonda_pll_disable()
2043 /* Place the PLL mode in OFF state */ in clk_zonda_pll_disable()
2044 regmap_write(regmap, PLL_OPMODE(pll), 0x0); in clk_zonda_pll_disable()
2050 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_set_rate() local
2053 u32 l, alpha_width = pll_alpha_width(pll); in clk_zonda_pll_set_rate()
2063 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_zonda_pll_set_rate()
2064 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_zonda_pll_set_rate()
2069 /* Read stay in cfa mode */ in clk_zonda_pll_set_rate()
2070 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); in clk_zonda_pll_set_rate()
2072 /* If cfa mode then poll for freq lock */ in clk_zonda_pll_set_rate()
2074 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_set_rate()
2076 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_set_rate()
2080 /* Wait for PLL output to stabilize */ in clk_zonda_pll_set_rate()
2095 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_evo_pll_configure() argument
2098 u32 lval = config->l; in clk_lucid_evo_pll_configure()
2101 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_evo_pll_configure()
2102 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_evo_pll_configure()
2103 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_evo_pll_configure()
2104 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_evo_pll_configure()
2105 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2106 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_evo_pll_configure()
2107 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_evo_pll_configure()
2108 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_evo_pll_configure()
2109 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_evo_pll_configure()
2110 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2111 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_evo_pll_configure()
2113 /* Disable PLL output */ in clk_lucid_evo_pll_configure()
2114 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_evo_pll_configure()
2116 /* Set operation mode to STANDBY and de-assert the reset */ in clk_lucid_evo_pll_configure()
2117 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_evo_pll_configure()
2118 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_evo_pll_configure()
2124 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_enable() local
2125 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_enable()
2129 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_evo_enable()
2133 /* If in FSM mode, just vote for it */ in alpha_pll_lucid_evo_enable()
2138 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2141 /* Check if PLL is already enabled */ in alpha_pll_lucid_evo_enable()
2142 ret = trion_pll_is_enabled(pll, regmap); in alpha_pll_lucid_evo_enable()
2146 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); in alpha_pll_lucid_evo_enable()
2150 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_evo_enable()
2154 /* Set operation mode to RUN */ in alpha_pll_lucid_evo_enable()
2155 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_evo_enable()
2157 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2161 /* Enable the PLL outputs */ in alpha_pll_lucid_evo_enable()
2162 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_evo_enable()
2166 /* Enable the global PLL outputs */ in alpha_pll_lucid_evo_enable()
2167 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_evo_enable()
2178 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_disable() local
2179 struct regmap *regmap = pll->clkr.regmap; in _alpha_pll_lucid_evo_disable()
2183 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in _alpha_pll_lucid_evo_disable()
2187 /* If in FSM mode, just unvote it */ in _alpha_pll_lucid_evo_disable()
2193 /* Disable the global PLL output */ in _alpha_pll_lucid_evo_disable()
2194 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in _alpha_pll_lucid_evo_disable()
2198 /* Disable the PLL outputs */ in _alpha_pll_lucid_evo_disable()
2199 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in _alpha_pll_lucid_evo_disable()
2203 /* Place the PLL mode in STANDBY */ in _alpha_pll_lucid_evo_disable()
2204 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in _alpha_pll_lucid_evo_disable()
2207 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); in _alpha_pll_lucid_evo_disable()
2212 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_prepare() local
2218 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in _alpha_pll_lucid_evo_prepare()
2224 return -EINVAL; in _alpha_pll_lucid_evo_prepare()
2258 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_recalc_rate() local
2259 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_recalc_rate()
2262 regmap_read(regmap, PLL_L_VAL(pll), &l); in alpha_pll_lucid_evo_recalc_rate()
2264 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); in alpha_pll_lucid_evo_recalc_rate()
2266 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); in alpha_pll_lucid_evo_recalc_rate()
2313 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_rivian_evo_pll_configure() argument
2316 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_rivian_evo_pll_configure()
2317 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_rivian_evo_pll_configure()
2318 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_rivian_evo_pll_configure()
2319 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_rivian_evo_pll_configure()
2320 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_rivian_evo_pll_configure()
2321 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_rivian_evo_pll_configure()
2322 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_rivian_evo_pll_configure()
2323 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_rivian_evo_pll_configure()
2325 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_rivian_evo_pll_configure()
2327 regmap_update_bits(regmap, PLL_MODE(pll), in clk_rivian_evo_pll_configure()
2336 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_recalc_rate() local
2339 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_rivian_evo_pll_recalc_rate()
2347 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_round_rate() local
2353 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_rivian_evo_pll_round_rate()
2356 min_freq = pll->vco_table[0].min_freq; in clk_rivian_evo_pll_round_rate()
2357 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_rivian_evo_pll_round_rate()
2371 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_stromer_pll_configure() argument
2376 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_stromer_pll_configure()
2377 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_stromer_pll_configure()
2378 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_stromer_pll_configure()
2380 if (pll_has_64bit_config(pll)) in clk_stromer_pll_configure()
2381 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_stromer_pll_configure()
2382 config->config_ctl_hi_val); in clk_stromer_pll_configure()
2384 if (pll_alpha_width(pll) > 32) in clk_stromer_pll_configure()
2385 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_stromer_pll_configure()
2387 val = config->main_output_mask; in clk_stromer_pll_configure()
2388 val |= config->aux_output_mask; in clk_stromer_pll_configure()
2389 val |= config->aux2_output_mask; in clk_stromer_pll_configure()
2390 val |= config->early_output_mask; in clk_stromer_pll_configure()
2391 val |= config->pre_div_val; in clk_stromer_pll_configure()
2392 val |= config->post_div_val; in clk_stromer_pll_configure()
2393 val |= config->vco_val; in clk_stromer_pll_configure()
2394 val |= config->alpha_en_mask; in clk_stromer_pll_configure()
2395 val |= config->alpha_mode_mask; in clk_stromer_pll_configure()
2397 mask = config->main_output_mask; in clk_stromer_pll_configure()
2398 mask |= config->aux_output_mask; in clk_stromer_pll_configure()
2399 mask |= config->aux2_output_mask; in clk_stromer_pll_configure()
2400 mask |= config->early_output_mask; in clk_stromer_pll_configure()
2401 mask |= config->pre_div_mask; in clk_stromer_pll_configure()
2402 mask |= config->post_div_mask; in clk_stromer_pll_configure()
2403 mask |= config->vco_mask; in clk_stromer_pll_configure()
2404 mask |= config->alpha_en_mask; in clk_stromer_pll_configure()
2405 mask |= config->alpha_mode_mask; in clk_stromer_pll_configure()
2407 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_stromer_pll_configure()
2409 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ in clk_stromer_pll_configure()
2410 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; in clk_stromer_pll_configure()
2411 val_u |= config->lock_det; in clk_stromer_pll_configure()
2413 mask_u = config->status_mask; in clk_stromer_pll_configure()
2414 mask_u |= config->lock_det; in clk_stromer_pll_configure()
2416 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); in clk_stromer_pll_configure()
2417 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_stromer_pll_configure()
2418 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_stromer_pll_configure()
2420 if (pll->flags & SUPPORTS_FSM_MODE) in clk_stromer_pll_configure()
2421 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_stromer_pll_configure()
2431 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, in clk_alpha_pll_stromer_determine_rate()
2440 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_set_rate() local
2447 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_set_rate()
2448 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_set_rate()
2449 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_set_rate()
2452 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_set_rate()
2459 * Stromer PLL supports Dynamic programming. in clk_alpha_pll_stromer_set_rate()
2460 * It allows the PLL frequency to be changed on-the-fly without first in clk_alpha_pll_stromer_set_rate()
2463 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in clk_alpha_pll_stromer_set_rate()
2466 ret = wait_for_pll_update(pll); in clk_alpha_pll_stromer_set_rate()
2470 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_set_rate()
2487 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_plus_set_rate() local
2488 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_stromer_plus_set_rate()
2494 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); in clk_alpha_pll_stromer_plus_set_rate()
2498 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); in clk_alpha_pll_stromer_plus_set_rate()
2503 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_plus_set_rate()
2506 a <<= alpha_width - ALPHA_BITWIDTH; in clk_alpha_pll_stromer_plus_set_rate()
2508 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_plus_set_rate()
2509 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_plus_set_rate()
2512 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); in clk_alpha_pll_stromer_plus_set_rate()
2516 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, in clk_alpha_pll_stromer_plus_set_rate()
2522 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_plus_set_rate()
2524 pr_err("Wait for PLL enable lock failed [%s] %d\n", in clk_alpha_pll_stromer_plus_set_rate()
2530 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, in clk_alpha_pll_stromer_plus_set_rate()