Lines Matching +full:0 +full:x12010
43 { 249600000, 2000000000, 0 },
47 .offset = 0x0,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
66 { 0x0, 1 },
67 { 0x1, 2 },
68 { 0x3, 4 },
69 { 0x7, 8 },
74 .offset = 0x0,
89 .offset = 0x1000,
94 .enable_reg = 0x52000,
108 .offset = 0x76000,
113 .enable_reg = 0x52000,
127 .offset = 0x1a000,
132 .enable_reg = 0x52000,
146 { P_BI_TCXO, 0 },
158 { P_BI_TCXO, 0 },
172 { P_BI_TCXO, 0 },
182 { P_BI_TCXO, 0 },
202 { P_BI_TCXO, 0 },
210 { P_BI_TCXO, 0 },
220 { P_BI_TCXO, 0 },
234 { P_BI_TCXO, 0 },
250 { P_BI_TCXO, 0 },
264 F(19200000, P_BI_TCXO, 1, 0, 0),
265 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
266 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
271 .cmd_rcgr = 0x48014,
272 .mnd_width = 0,
286 F(19200000, P_BI_TCXO, 1, 0, 0),
287 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
288 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
289 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
294 .cmd_rcgr = 0x6038,
295 .mnd_width = 0,
311 F(19200000, P_BI_TCXO, 1, 0, 0),
312 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
313 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
314 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
315 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
320 .cmd_rcgr = 0x601c,
335 F(19200000, P_BI_TCXO, 1, 0, 0),
336 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
337 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
338 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
339 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
344 .cmd_rcgr = 0x64004,
359 .cmd_rcgr = 0x65004,
374 .cmd_rcgr = 0x66004,
389 .cmd_rcgr = 0xbe004,
404 .cmd_rcgr = 0xbf004,
419 F(19200000, P_BI_TCXO, 1, 0, 0),
420 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
421 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
422 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
423 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
424 F(403000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
425 F(533000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
430 .cmd_rcgr = 0x4d014,
431 .mnd_width = 0,
445 F(9600000, P_BI_TCXO, 2, 0, 0),
446 F(19200000, P_BI_TCXO, 1, 0, 0),
451 .cmd_rcgr = 0x6b02c,
466 .cmd_rcgr = 0x8d02c,
481 .cmd_rcgr = 0x9d02c,
496 .cmd_rcgr = 0xa302c,
511 F(19200000, P_BI_TCXO, 1, 0, 0),
512 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
517 .cmd_rcgr = 0x6f014,
518 .mnd_width = 0,
532 F(9600000, P_BI_TCXO, 2, 0, 0),
533 F(19200000, P_BI_TCXO, 1, 0, 0),
534 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
539 .cmd_rcgr = 0x33010,
540 .mnd_width = 0,
554 F(19200000, P_BI_TCXO, 1, 0, 0),
555 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
556 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
557 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
562 .cmd_rcgr = 0x4a00c,
563 .mnd_width = 0,
577 .cmd_rcgr = 0x4b008,
578 .mnd_width = 0,
594 F(19200000, P_BI_TCXO, 1, 0, 0),
598 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
600 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
603 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
607 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
613 .cmd_rcgr = 0x17148,
628 .cmd_rcgr = 0x17278,
643 .cmd_rcgr = 0x173a8,
658 .cmd_rcgr = 0x174d8,
673 .cmd_rcgr = 0x17608,
688 .cmd_rcgr = 0x17738,
703 .cmd_rcgr = 0x17868,
718 .cmd_rcgr = 0x17998,
733 .cmd_rcgr = 0x18148,
748 .cmd_rcgr = 0x18278,
763 .cmd_rcgr = 0x183a8,
778 .cmd_rcgr = 0x184d8,
793 .cmd_rcgr = 0x18608,
808 .cmd_rcgr = 0x18738,
823 .cmd_rcgr = 0x1e148,
838 .cmd_rcgr = 0x1e278,
853 .cmd_rcgr = 0x1e3a8,
868 .cmd_rcgr = 0x1e4d8,
883 .cmd_rcgr = 0x1e608,
898 .cmd_rcgr = 0x1e738,
914 F(9600000, P_BI_TCXO, 2, 0, 0),
915 F(19200000, P_BI_TCXO, 1, 0, 0),
917 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
918 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
919 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
924 .cmd_rcgr = 0x1400c,
940 F(9600000, P_BI_TCXO, 2, 0, 0),
941 F(19200000, P_BI_TCXO, 1, 0, 0),
942 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
943 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
944 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
949 .cmd_rcgr = 0x1600c,
969 .cmd_rcgr = 0x36010,
984 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
985 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
986 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
987 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
992 .cmd_rcgr = 0xa2020,
1007 .cmd_rcgr = 0xa2060,
1008 .mnd_width = 0,
1022 F(19200000, P_BI_TCXO, 1, 0, 0),
1027 .cmd_rcgr = 0xa2094,
1028 .mnd_width = 0,
1042 .cmd_rcgr = 0xa2078,
1043 .mnd_width = 0,
1057 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1058 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1059 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1060 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1061 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1066 .cmd_rcgr = 0x75020,
1081 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1082 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1083 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1088 .cmd_rcgr = 0x75060,
1089 .mnd_width = 0,
1103 .cmd_rcgr = 0x75094,
1104 .mnd_width = 0,
1118 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1119 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1120 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1125 .cmd_rcgr = 0x75078,
1126 .mnd_width = 0,
1140 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1141 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1142 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1143 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1144 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1149 .cmd_rcgr = 0x77020,
1164 .cmd_rcgr = 0x77060,
1165 .mnd_width = 0,
1179 .cmd_rcgr = 0x77094,
1180 .mnd_width = 0,
1194 .cmd_rcgr = 0x77078,
1195 .mnd_width = 0,
1209 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1210 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1211 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1212 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1213 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1218 .cmd_rcgr = 0xa601c,
1233 F(19200000, P_BI_TCXO, 1, 0, 0),
1234 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1235 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1236 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1241 .cmd_rcgr = 0xa6034,
1242 .mnd_width = 0,
1256 .cmd_rcgr = 0xf01c,
1271 .cmd_rcgr = 0xf034,
1272 .mnd_width = 0,
1286 .cmd_rcgr = 0x1001c,
1301 .cmd_rcgr = 0x10034,
1302 .mnd_width = 0,
1316 .cmd_rcgr = 0xa6068,
1317 .mnd_width = 0,
1331 .cmd_rcgr = 0xf060,
1332 .mnd_width = 0,
1346 .cmd_rcgr = 0x10060,
1347 .mnd_width = 0,
1361 .halt_reg = 0x90018,
1364 .enable_reg = 0x90018,
1365 .enable_mask = BIT(0),
1374 .halt_reg = 0x750c0,
1376 .hwcg_reg = 0x750c0,
1379 .enable_reg = 0x750c0,
1380 .enable_mask = BIT(0),
1394 .halt_reg = 0x750c0,
1396 .hwcg_reg = 0x750c0,
1399 .enable_reg = 0x750c0,
1414 .halt_reg = 0x770c0,
1416 .hwcg_reg = 0x770c0,
1419 .enable_reg = 0x770c0,
1420 .enable_mask = BIT(0),
1434 .halt_reg = 0x770c0,
1436 .hwcg_reg = 0x770c0,
1439 .enable_reg = 0x770c0,
1454 .halt_reg = 0xa6084,
1457 .enable_reg = 0xa6084,
1458 .enable_mask = BIT(0),
1472 .halt_reg = 0xf07c,
1475 .enable_reg = 0xf07c,
1476 .enable_mask = BIT(0),
1490 .halt_reg = 0x1007c,
1493 .enable_reg = 0x1007c,
1494 .enable_mask = BIT(0),
1508 .halt_reg = 0x38004,
1510 .hwcg_reg = 0x38004,
1513 .enable_reg = 0x52004,
1523 .halt_reg = 0xb030,
1526 .enable_reg = 0xb030,
1527 .enable_mask = BIT(0),
1536 .halt_reg = 0xb034,
1539 .enable_reg = 0xb034,
1540 .enable_mask = BIT(0),
1549 .halt_reg = 0xa609c,
1552 .enable_reg = 0xa609c,
1553 .enable_mask = BIT(0),
1567 .halt_reg = 0xf078,
1570 .enable_reg = 0xf078,
1571 .enable_mask = BIT(0),
1585 .halt_reg = 0x10078,
1588 .enable_reg = 0x10078,
1589 .enable_mask = BIT(0),
1604 .halt_reg = 0x48000,
1607 .enable_reg = 0x52004,
1622 .halt_reg = 0x48008,
1625 .enable_reg = 0x48008,
1626 .enable_mask = BIT(0),
1635 .halt_reg = 0x71154,
1638 .enable_reg = 0x71154,
1639 .enable_mask = BIT(0),
1648 .halt_reg = 0xb038,
1651 .enable_reg = 0xb038,
1652 .enable_mask = BIT(0),
1661 .halt_reg = 0xb03c,
1664 .enable_reg = 0xb03c,
1665 .enable_mask = BIT(0),
1674 .halt_reg = 0x6010,
1677 .enable_reg = 0x6010,
1678 .enable_mask = BIT(0),
1687 .halt_reg = 0x6034,
1690 .enable_reg = 0x6034,
1691 .enable_mask = BIT(0),
1705 .halt_reg = 0x6018,
1708 .enable_reg = 0x6018,
1709 .enable_mask = BIT(0),
1723 .halt_reg = 0x6014,
1725 .hwcg_reg = 0x6014,
1728 .enable_reg = 0x6014,
1729 .enable_mask = BIT(0),
1738 .halt_reg = 0x64000,
1741 .enable_reg = 0x64000,
1742 .enable_mask = BIT(0),
1756 .halt_reg = 0x65000,
1759 .enable_reg = 0x65000,
1760 .enable_mask = BIT(0),
1774 .halt_reg = 0x66000,
1777 .enable_reg = 0x66000,
1778 .enable_mask = BIT(0),
1792 .halt_reg = 0xbe000,
1795 .enable_reg = 0xbe000,
1796 .enable_mask = BIT(0),
1810 .halt_reg = 0xbf000,
1813 .enable_reg = 0xbf000,
1814 .enable_mask = BIT(0),
1830 .enable_reg = 0x52004,
1845 .enable_reg = 0x52004,
1860 .halt_reg = 0x7100c,
1863 .enable_reg = 0x7100c,
1864 .enable_mask = BIT(0),
1873 .halt_reg = 0x71018,
1876 .enable_reg = 0x71018,
1877 .enable_mask = BIT(0),
1886 .halt_reg = 0x4d010,
1889 .enable_reg = 0x4d010,
1890 .enable_mask = BIT(0),
1899 .halt_reg = 0x4d008,
1902 .enable_reg = 0x4d008,
1903 .enable_mask = BIT(0),
1919 .enable_reg = 0x52004,
1934 .enable_reg = 0x52004,
1949 .halt_reg = 0x4d00c,
1952 .enable_reg = 0x4d00c,
1953 .enable_mask = BIT(0),
1962 .halt_reg = 0x6f02c,
1965 .enable_reg = 0x6f02c,
1966 .enable_mask = BIT(0),
1980 .halt_reg = 0x6f030,
1983 .enable_reg = 0x6f030,
1984 .enable_mask = BIT(0),
1998 .halt_reg = 0x6f034,
2001 .enable_reg = 0x6f034,
2002 .enable_mask = BIT(0),
2016 .halt_reg = 0x6f038,
2019 .enable_reg = 0x6f038,
2020 .enable_mask = BIT(0),
2034 .halt_reg = 0x6b020,
2037 .enable_reg = 0x5200c,
2052 .halt_reg = 0x6b01c,
2054 .hwcg_reg = 0x6b01c,
2057 .enable_reg = 0x5200c,
2067 .halt_reg = 0x8c00c,
2070 .enable_reg = 0x8c00c,
2071 .enable_mask = BIT(0),
2080 .halt_reg = 0x6b018,
2083 .enable_reg = 0x5200c,
2093 .halt_reg = 0x6b024,
2096 .enable_reg = 0x5200c,
2106 .halt_reg = 0x6b014,
2108 .hwcg_reg = 0x6b014,
2111 .enable_reg = 0x5200c,
2112 .enable_mask = BIT(0),
2121 .halt_reg = 0x6b010,
2124 .enable_reg = 0x5200c,
2134 .halt_reg = 0x8d020,
2137 .enable_reg = 0x52004,
2152 .halt_reg = 0x8d01c,
2154 .hwcg_reg = 0x8d01c,
2157 .enable_reg = 0x52004,
2167 .halt_reg = 0x8c02c,
2170 .enable_reg = 0x8c02c,
2171 .enable_mask = BIT(0),
2180 .halt_reg = 0x8d018,
2183 .enable_reg = 0x52004,
2193 .halt_reg = 0x8d024,
2196 .enable_reg = 0x52004,
2206 .halt_reg = 0x8d014,
2208 .hwcg_reg = 0x8d014,
2211 .enable_reg = 0x52004,
2221 .halt_reg = 0x8d010,
2224 .enable_reg = 0x52004,
2234 .halt_reg = 0x9d020,
2237 .enable_reg = 0x52014,
2252 .halt_reg = 0x9d01c,
2254 .hwcg_reg = 0x9d01c,
2257 .enable_reg = 0x52014,
2267 .halt_reg = 0x8c014,
2270 .enable_reg = 0x8c014,
2271 .enable_mask = BIT(0),
2280 .halt_reg = 0x9d018,
2283 .enable_reg = 0x52014,
2293 .halt_reg = 0x9d024,
2296 .enable_reg = 0x52014,
2306 .halt_reg = 0x9d014,
2308 .hwcg_reg = 0x9d014,
2311 .enable_reg = 0x52014,
2321 .halt_reg = 0x9d010,
2324 .enable_reg = 0x52014,
2334 .halt_reg = 0xa3020,
2337 .enable_reg = 0x52014,
2352 .halt_reg = 0xa301c,
2354 .hwcg_reg = 0xa301c,
2357 .enable_reg = 0x52014,
2367 .halt_reg = 0x8c018,
2370 .enable_reg = 0x8c018,
2371 .enable_mask = BIT(0),
2380 .halt_reg = 0xa3018,
2383 .enable_reg = 0x52014,
2393 .halt_reg = 0xa3024,
2396 .enable_reg = 0x52014,
2406 .halt_reg = 0xa3014,
2408 .hwcg_reg = 0xa3014,
2411 .enable_reg = 0x52014,
2421 .halt_reg = 0xa3010,
2424 .enable_reg = 0x52014,
2434 .halt_reg = 0x6f004,
2437 .enable_reg = 0x6f004,
2438 .enable_mask = BIT(0),
2452 .halt_reg = 0x3300c,
2455 .enable_reg = 0x3300c,
2456 .enable_mask = BIT(0),
2470 .halt_reg = 0x33004,
2472 .hwcg_reg = 0x33004,
2475 .enable_reg = 0x33004,
2476 .enable_mask = BIT(0),
2485 .halt_reg = 0x33008,
2488 .enable_reg = 0x33008,
2489 .enable_mask = BIT(0),
2498 .halt_reg = 0x34004,
2501 .enable_reg = 0x52004,
2511 .halt_reg = 0xb018,
2513 .hwcg_reg = 0xb018,
2516 .enable_reg = 0xb018,
2517 .enable_mask = BIT(0),
2526 .halt_reg = 0xb01c,
2528 .hwcg_reg = 0xb01c,
2531 .enable_reg = 0xb01c,
2532 .enable_mask = BIT(0),
2541 .halt_reg = 0xb020,
2543 .hwcg_reg = 0xb020,
2546 .enable_reg = 0xb020,
2547 .enable_mask = BIT(0),
2556 .halt_reg = 0xb010,
2558 .hwcg_reg = 0xb010,
2561 .enable_reg = 0xb010,
2562 .enable_mask = BIT(0),
2571 .halt_reg = 0xb014,
2573 .hwcg_reg = 0xb014,
2576 .enable_reg = 0xb014,
2577 .enable_mask = BIT(0),
2586 .halt_reg = 0x4a004,
2589 .enable_reg = 0x4a004,
2590 .enable_mask = BIT(0),
2599 .halt_reg = 0x4a008,
2602 .enable_reg = 0x4a008,
2603 .enable_mask = BIT(0),
2617 .halt_reg = 0x4b000,
2620 .enable_reg = 0x4b000,
2621 .enable_mask = BIT(0),
2630 .halt_reg = 0x4b004,
2633 .enable_reg = 0x4b004,
2634 .enable_mask = BIT(0),
2648 .halt_reg = 0x17144,
2651 .enable_reg = 0x5200c,
2666 .halt_reg = 0x17274,
2669 .enable_reg = 0x5200c,
2684 .halt_reg = 0x173a4,
2687 .enable_reg = 0x5200c,
2702 .halt_reg = 0x174d4,
2705 .enable_reg = 0x5200c,
2720 .halt_reg = 0x17604,
2723 .enable_reg = 0x5200c,
2738 .halt_reg = 0x17734,
2741 .enable_reg = 0x5200c,
2756 .halt_reg = 0x17864,
2759 .enable_reg = 0x5200c,
2774 .halt_reg = 0x17994,
2777 .enable_reg = 0x5200c,
2792 .halt_reg = 0x18144,
2795 .enable_reg = 0x5200c,
2810 .halt_reg = 0x18274,
2813 .enable_reg = 0x5200c,
2828 .halt_reg = 0x183a4,
2831 .enable_reg = 0x5200c,
2846 .halt_reg = 0x184d4,
2849 .enable_reg = 0x5200c,
2864 .halt_reg = 0x18604,
2867 .enable_reg = 0x5200c,
2882 .halt_reg = 0x18734,
2885 .enable_reg = 0x5200c,
2900 .halt_reg = 0x1e144,
2903 .enable_reg = 0x52014,
2918 .halt_reg = 0x1e274,
2921 .enable_reg = 0x52014,
2936 .halt_reg = 0x1e3a4,
2939 .enable_reg = 0x52014,
2954 .halt_reg = 0x1e4d4,
2957 .enable_reg = 0x52014,
2972 .halt_reg = 0x1e604,
2975 .enable_reg = 0x52014,
2990 .halt_reg = 0x1e734,
2993 .enable_reg = 0x52014,
3008 .halt_reg = 0x17004,
3011 .enable_reg = 0x5200c,
3021 .halt_reg = 0x17008,
3023 .hwcg_reg = 0x17008,
3026 .enable_reg = 0x5200c,
3036 .halt_reg = 0x18004,
3039 .enable_reg = 0x5200c,
3049 .halt_reg = 0x18008,
3051 .hwcg_reg = 0x18008,
3054 .enable_reg = 0x5200c,
3064 .halt_reg = 0x1e004,
3067 .enable_reg = 0x52014,
3077 .halt_reg = 0x1e008,
3079 .hwcg_reg = 0x1e008,
3082 .enable_reg = 0x52014,
3092 .halt_reg = 0x14008,
3095 .enable_reg = 0x14008,
3096 .enable_mask = BIT(0),
3105 .halt_reg = 0x14004,
3108 .enable_reg = 0x14004,
3109 .enable_mask = BIT(0),
3123 .halt_reg = 0x16008,
3126 .enable_reg = 0x16008,
3127 .enable_mask = BIT(0),
3136 .halt_reg = 0x16004,
3139 .enable_reg = 0x16004,
3140 .enable_mask = BIT(0),
3155 .halt_reg = 0x4819c,
3158 .enable_reg = 0x52004,
3159 .enable_mask = BIT(0),
3173 .halt_reg = 0x36004,
3176 .enable_reg = 0x36004,
3177 .enable_mask = BIT(0),
3186 .halt_reg = 0x3600c,
3189 .enable_reg = 0x3600c,
3190 .enable_mask = BIT(0),
3199 .halt_reg = 0x36008,
3202 .enable_reg = 0x36008,
3203 .enable_mask = BIT(0),
3217 .halt_reg = 0xa2014,
3219 .hwcg_reg = 0xa2014,
3222 .enable_reg = 0xa2014,
3223 .enable_mask = BIT(0),
3232 .halt_reg = 0xa2010,
3234 .hwcg_reg = 0xa2010,
3237 .enable_reg = 0xa2010,
3238 .enable_mask = BIT(0),
3252 .halt_reg = 0xa205c,
3254 .hwcg_reg = 0xa205c,
3257 .enable_reg = 0xa205c,
3258 .enable_mask = BIT(0),
3272 .halt_reg = 0xa2090,
3274 .hwcg_reg = 0xa2090,
3277 .enable_reg = 0xa2090,
3278 .enable_mask = BIT(0),
3292 .halt_reg = 0xa201c,
3295 .enable_reg = 0xa201c,
3296 .enable_mask = BIT(0),
3305 .halt_reg = 0xa20ac,
3308 .enable_reg = 0xa20ac,
3309 .enable_mask = BIT(0),
3318 .halt_reg = 0xa2018,
3321 .enable_reg = 0xa2018,
3322 .enable_mask = BIT(0),
3331 .halt_reg = 0xa2058,
3333 .hwcg_reg = 0xa2058,
3336 .enable_reg = 0xa2058,
3337 .enable_mask = BIT(0),
3351 .halt_reg = 0x75014,
3353 .hwcg_reg = 0x75014,
3356 .enable_reg = 0x75014,
3357 .enable_mask = BIT(0),
3366 .halt_reg = 0x75010,
3368 .hwcg_reg = 0x75010,
3371 .enable_reg = 0x75010,
3372 .enable_mask = BIT(0),
3386 .halt_reg = 0x75010,
3388 .hwcg_reg = 0x75010,
3391 .enable_reg = 0x75010,
3406 .halt_reg = 0x7505c,
3408 .hwcg_reg = 0x7505c,
3411 .enable_reg = 0x7505c,
3412 .enable_mask = BIT(0),
3426 .halt_reg = 0x7505c,
3428 .hwcg_reg = 0x7505c,
3431 .enable_reg = 0x7505c,
3446 .halt_reg = 0x75090,
3448 .hwcg_reg = 0x75090,
3451 .enable_reg = 0x75090,
3452 .enable_mask = BIT(0),
3466 .halt_reg = 0x75090,
3468 .hwcg_reg = 0x75090,
3471 .enable_reg = 0x75090,
3486 .halt_reg = 0x7501c,
3489 .enable_reg = 0x7501c,
3490 .enable_mask = BIT(0),
3499 .halt_reg = 0x750ac,
3502 .enable_reg = 0x750ac,
3503 .enable_mask = BIT(0),
3512 .halt_reg = 0x75018,
3515 .enable_reg = 0x75018,
3516 .enable_mask = BIT(0),
3525 .halt_reg = 0x75058,
3527 .hwcg_reg = 0x75058,
3530 .enable_reg = 0x75058,
3531 .enable_mask = BIT(0),
3545 .halt_reg = 0x75058,
3547 .hwcg_reg = 0x75058,
3550 .enable_reg = 0x75058,
3565 .halt_reg = 0x77014,
3567 .hwcg_reg = 0x77014,
3570 .enable_reg = 0x77014,
3571 .enable_mask = BIT(0),
3580 .halt_reg = 0x77010,
3582 .hwcg_reg = 0x77010,
3585 .enable_reg = 0x77010,
3586 .enable_mask = BIT(0),
3600 .halt_reg = 0x77010,
3602 .hwcg_reg = 0x77010,
3605 .enable_reg = 0x77010,
3620 .halt_reg = 0x7705c,
3622 .hwcg_reg = 0x7705c,
3625 .enable_reg = 0x7705c,
3626 .enable_mask = BIT(0),
3640 .halt_reg = 0x7705c,
3642 .hwcg_reg = 0x7705c,
3645 .enable_reg = 0x7705c,
3660 .halt_reg = 0x77090,
3662 .hwcg_reg = 0x77090,
3665 .enable_reg = 0x77090,
3666 .enable_mask = BIT(0),
3680 .halt_reg = 0x77090,
3682 .hwcg_reg = 0x77090,
3685 .enable_reg = 0x77090,
3700 .halt_reg = 0x7701c,
3703 .enable_reg = 0x7701c,
3704 .enable_mask = BIT(0),
3713 .halt_reg = 0x770ac,
3716 .enable_reg = 0x770ac,
3717 .enable_mask = BIT(0),
3726 .halt_reg = 0x77018,
3729 .enable_reg = 0x77018,
3730 .enable_mask = BIT(0),
3739 .halt_reg = 0x77058,
3741 .hwcg_reg = 0x77058,
3744 .enable_reg = 0x77058,
3745 .enable_mask = BIT(0),
3759 .halt_reg = 0x77058,
3761 .hwcg_reg = 0x77058,
3764 .enable_reg = 0x77058,
3779 .halt_reg = 0xa6010,
3782 .enable_reg = 0xa6010,
3783 .enable_mask = BIT(0),
3796 .halt_reg = 0xa6018,
3799 .enable_reg = 0xa6018,
3800 .enable_mask = BIT(0),
3814 .halt_reg = 0xa6014,
3817 .enable_reg = 0xa6014,
3818 .enable_mask = BIT(0),
3827 .halt_reg = 0xf010,
3830 .enable_reg = 0xf010,
3831 .enable_mask = BIT(0),
3844 .halt_reg = 0xf018,
3847 .enable_reg = 0xf018,
3848 .enable_mask = BIT(0),
3862 .halt_reg = 0xf014,
3865 .enable_reg = 0xf014,
3866 .enable_mask = BIT(0),
3875 .halt_reg = 0x10010,
3878 .enable_reg = 0x10010,
3879 .enable_mask = BIT(0),
3892 .halt_reg = 0x10018,
3895 .enable_reg = 0x10018,
3896 .enable_mask = BIT(0),
3910 .halt_reg = 0x10014,
3913 .enable_reg = 0x10014,
3914 .enable_mask = BIT(0),
3923 .halt_reg = 0xa6050,
3926 .enable_reg = 0xa6050,
3927 .enable_mask = BIT(0),
3941 .halt_reg = 0xa6054,
3944 .enable_reg = 0xa6054,
3945 .enable_mask = BIT(0),
3959 .halt_reg = 0xa6058,
3962 .enable_reg = 0xa6058,
3963 .enable_mask = BIT(0),
3972 .halt_reg = 0xa605c,
3975 .enable_reg = 0xa605c,
3976 .enable_mask = BIT(0),
3985 .halt_reg = 0x8c008,
3988 .enable_reg = 0x8c008,
3989 .enable_mask = BIT(0),
3998 .halt_reg = 0xf050,
4001 .enable_reg = 0xf050,
4002 .enable_mask = BIT(0),
4016 .halt_reg = 0xf054,
4019 .enable_reg = 0xf054,
4020 .enable_mask = BIT(0),
4034 .halt_reg = 0xf058,
4037 .enable_reg = 0xf058,
4038 .enable_mask = BIT(0),
4047 .halt_reg = 0x8c028,
4050 .enable_reg = 0x8c028,
4051 .enable_mask = BIT(0),
4060 .halt_reg = 0x10050,
4063 .enable_reg = 0x10050,
4064 .enable_mask = BIT(0),
4078 .halt_reg = 0x10054,
4081 .enable_reg = 0x10054,
4082 .enable_mask = BIT(0),
4096 .halt_reg = 0x10058,
4099 .enable_reg = 0x10058,
4100 .enable_mask = BIT(0),
4109 .halt_reg = 0xb024,
4112 .enable_reg = 0xb024,
4113 .enable_mask = BIT(0),
4122 .halt_reg = 0xb028,
4125 .enable_reg = 0xb028,
4126 .enable_mask = BIT(0),
4135 .halt_reg = 0xb02c,
4138 .enable_reg = 0xb02c,
4139 .enable_mask = BIT(0),
4148 .gdscr = 0x10004,
4157 .gdscr = 0x6004,
4166 .gdscr = 0xf004,
4175 .gdscr = 0x6b004,
4184 .gdscr = 0x75004,
4193 .gdscr = 0x77004,
4202 .gdscr = 0x8d004,
4211 .gdscr = 0x9d004,
4220 .gdscr = 0xa2004,
4229 .gdscr = 0xa3004,
4238 .gdscr = 0xa6004,
4489 [GCC_EMAC_BCR] = { 0x6000 },
4490 [GCC_GPU_BCR] = { 0x71000 },
4491 [GCC_MMSS_BCR] = { 0xb000 },
4492 [GCC_NPU_BCR] = { 0x4d000 },
4493 [GCC_PCIE_0_BCR] = { 0x6b000 },
4494 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
4495 [GCC_PCIE_1_BCR] = { 0x8d000 },
4496 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
4497 [GCC_PCIE_2_BCR] = { 0x9d000 },
4498 [GCC_PCIE_2_PHY_BCR] = { 0xa701c },
4499 [GCC_PCIE_3_BCR] = { 0xa3000 },
4500 [GCC_PCIE_3_PHY_BCR] = { 0xa801c },
4501 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
4502 [GCC_PDM_BCR] = { 0x33000 },
4503 [GCC_PRNG_BCR] = { 0x34000 },
4504 [GCC_QSPI_1_BCR] = { 0x4a000 },
4505 [GCC_QSPI_BCR] = { 0x24008 },
4506 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
4507 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
4508 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
4509 [GCC_QUSB2PHY_5_BCR] = { 0x12010 },
4510 [GCC_QUSB2PHY_MP0_BCR] = { 0x12008 },
4511 [GCC_QUSB2PHY_MP1_BCR] = { 0x1200c },
4512 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
4513 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
4514 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },
4515 [GCC_USB3_PHY_PRIM_SP1_BCR] = { 0x50004 },
4516 [GCC_USB3_DP_PHY_PRIM_SP0_BCR] = { 0x50010 },
4517 [GCC_USB3_DP_PHY_PRIM_SP1_BCR] = { 0x50014 },
4518 [GCC_USB3_PHY_SEC_BCR] = { 0x50018 },
4519 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
4520 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
4521 [GCC_SDCC2_BCR] = { 0x14000 },
4522 [GCC_SDCC4_BCR] = { 0x16000 },
4523 [GCC_TSIF_BCR] = { 0x36000 },
4524 [GCC_UFS_CARD_2_BCR] = { 0xa2000 },
4525 [GCC_UFS_CARD_BCR] = { 0x75000 },
4526 [GCC_UFS_PHY_BCR] = { 0x77000 },
4527 [GCC_USB30_MP_BCR] = { 0xa6000 },
4528 [GCC_USB30_PRIM_BCR] = { 0xf000 },
4529 [GCC_USB30_SEC_BCR] = { 0x10000 },
4530 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
4531 [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
4532 [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
4533 [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
4554 .max_register = 0xc0004,
4589 regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4590 regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4591 regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4592 regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4593 regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4594 regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4595 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4596 regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4597 regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4598 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4601 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sc8180x_probe()
4602 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sc8180x_probe()